Hi,
I'm using Incisive 13.20 .
I'm having a strange case that for $cds_get_analog_value(hierachy,"flow") , the result is a delay value of previous time step.
For example:
Time = 1e-06; I = 10e-06; I_cgav = 5e-06
Time = 2e-06; I = 15e-06; I_cgav = 10e-06
And it only happens for current assertion, for voltage assertion cds_get_analog_value works fine.
Is it a bug only on Incisive 13 and is it already fixed for later version?