ADE Explorer - Extracted DSPF Netlist - Probing Transient Current
Hi,In prelayout test bench, I am able to "save" and "probe" current terminals directly from a junction or port. For example, after running a transient simulation, I can do Results-->Direct...
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Clipping layer in Layout
The layout cell I am working on has a given P&R boundary. Over the cell area I inserted a set of uniformly distributed metal lines using the Mosaic feature. However, some metal lines go out of the...
View ArticlePVS requires pin Label to pass the LVS
Hello,I am newly shifted to the PVS tools of Cadence, and I used to have Assura.I am facing an issue of running the LVS from the PVS, that is it reuires me to add labels for my pins, otherwise, a...
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Incomplete DRC Results
I'm using the PVS DRC tool on Cadence version IC6.1.8-64b.500.9 and I noticed that some DRC errors are not reported but it looks like the settings should allow them to be reported. The seemingly...
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probing internal bus
Hello, I would like to probe 4 internal 8-bit buses from the testbench hierarchical level in post layout simulation.In order to do this, i use multiple deepprobes and fill in the path manually. See the...
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Using sampled pxf analysis to simulate deterministic jitter
The Rapid Adoption Kit "Deterministic Jitter Measurement using SpectreRF" (https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000009EVT2UAO) shows how a sampled pxf analysis can be used...
View ArticleUndo history cleared when saving layout
I've read some answers that cadence didn't have the option to change that, but those were answered like 7 years ago, is there any solution by now?
View ArticlePDK automation system
Does anyone know where to download PAS（PDK automation system）? Thank you.
View ArticleLVS complaining about lower level hierarchal design
Hello,I am at the chip level verification when the Assura LVS started to complain about mismatching in the lower level hierarchal design. To make it clear my highest chip-level design has four blocks...
View Articledouble counting of MOM capacitors in extracted view
Hi,I use Calibre for LVS and QRC for parasitic extraction. As it turns out, this results in double counting of MOM capacitors. QRC treats them as parasitcs and at the same time mom capacitor cells are...
View ArticleCell copy problem with layout view in Cadence Virtuoso
Hello,I am facing a problem when I copy some of my cells that has layout view. That is when I work on the layout of the copied cell it still modifies the original one and caused me a lot of troubles in...
View Articleproblem about hidding schematic in virtuoso
I have an analog block in virtuoso (no layout) and I wanna send the design block to others but hope that no detailed inner circuit (schematic) is shown there (only the pins are shown), is it possible?...
View ArticleUsing functions in Assembler global variables
HiI need to sweep the impedance of an analogLib port component including both resistance and the reactance parameters. To do this a little complex math is required to calculate R and X including...
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Signal doesn't reach full swing (0 -> VDD) in post-layout spectre...
Hi,I'm simulating a digital full-custom design using Spectre (20.1.0.298.isr9) in ADE Assembler (ICADVM20.1-64b.500.21).The layout is DRC and LVS clean. The extraction was done with Cablire (xACT, xACT...
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Fluid Guard Ring porting can't show correct layer
Hi! currently I tried use A foundry ported to B foundry,and find abnormal from Fluid Guard Ring issue,this Fluid Guard Ring just can't show the NPLUS layer I'm sure I recreate A and B foundry Fluid...
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Plotting from ADE Explorer (netl err)
Hi,When I run simulation in Maestro view (ADE Explorer), there is netlist error (netl err). Here is the error:ERROR(WIA-1175): Cannot plot waveform signals because no waveform data is available for...
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FFT of a signal
Hello,I want to measure the FFT of a clock signal but during measurement I am getting some unwanted result. I am using a 3 MHz clock signal and perform fft by Measurement -> Spectrum. Sampling...
View Articlerun multiple stb sim at the same time
Hi Guys,I am looking for the method to run multiple stb sim, e.g., different probes of stb, at the same time. Is that possible?BR
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Fatal error found by spectre during topology check.
I am trying to build verilogA code of MTJ in cadence. I got the following error. I am new to cadence . please help me to eliminate the error . Fatal error found by spectre during topology check. FATAL:...
View ArticleRe-run Unfinished/Error Points Problem
I had a license server failure with 12/193 runs not finishing. When I try to use the 'Re-run Unfinished/Error Points' option in the Assembler history the tool attempts to run all 193 points instead of...
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