I am trying to build verilogA code of MTJ in cadence. I got the following error. I am new to cadence . please help me to eliminate the error .
Fatal error found by spectre during topology check.
FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
I1:mz_flow (from net012 to 0)
I1:my_flow (from net14 to 0)
I1:mx_flow (from net13 to 0)
the schematic used is given below
