Hi,
In prelayout test bench, I am able to "save" and "probe" current terminals directly from a junction or port. For example, after running a transient simulation, I can do Results-->Direct Plot-->Transient Signal and plot the transient currently directly.
However, when I use a DSPF extracted netlist, I am unable to probe currents anymore.
Under "OUTPUTS --> SAVE ALL --> Save By Subckt" I have the modules for V, I, Pwr, and Ports saved with 3 levels of hierarchy but I am still unable to probe the current.
What is the best way to probe current using extracted netlist?
I am using Cadence Version 20.1 64bit, thank you in advance