I'm using the PVS DRC tool on Cadence version IC6.1.8-64b.500.9 and I noticed that some DRC errors are not reported but it looks like the settings should allow them to be reported. The seemingly relevant settings are:
- Output Limit: 1000
- Hierarchy Depth Limit: 32
- No special settings in configurator or include PVL
I'm seeing that some minimum metal area violations are reported but not others, for example:
There are two identical devices here with MET1 on the pcell gate connection. The minimum area violation on the left is reported but not on the right. Theses two devices are in the same level of hierarchy, in fact they are an arrayed instance as seen here:
I've highlighted the entire section relevant to minimum MET1 violations in the PVS DRC Debug tool:
As I fix the existing errors the tool does seem to find the additional errors eventually but this is a little bit concerning. As can be seen in the above screenshot there isn't some artificial limit per rule preventing additional errors from being reported as rule MET1.4 shows 7 errors. I've also had many more errors than shown in this example run so I don't believe there is any issue there. I've also double checked the rule deck files and there isn't anything suspicious there either. If anyone has any experience with this type of issue any insight would be appreciated.