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pin map error after pex analyse in calibre
hiI'm using 6.1.7 cadence and I completed the layout of my design.I have done DRC and lvs analyze without error but when I want to do pex analyze, after I did the calibre view setup I got this message...
View ArticlePSTB + PSS Analysis for dc-dc converter feedback loop stability
Hello Cadence community,I'm a newbie for using Cadence Virtuoso simulation bench to study the loop stability of a dc-dc converter. My setup is a dc voltage fed into a Full-bridge inverter and then...
View ArticlePlot Phase Noise of each sub-circuit from Calculator
Hi All,I am trying to analyze the phase noise of a VCO + Driver + Divider chain. I would like see how much phase noise is contributed by each sub-circuit. I can see the spot or integrated noise at each...
View ArticleCalculator: How to avoid interpolation when using spectrumMeasurement()?
Hi! Is it possible to avoid somehow the interpolation done by spectrumMeasurement()?Context: I would like to apply spectrumMeasurement() to waveforms produced by abCrossTwoWaves(). However, the...
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Layout of the technology cells are distorted
Hello,I wanted to work with my old designs which was in UMC180, however, when I opened the layouts in both virtuoso 618 and 617 I realized that the layouts are distorted. I can show you with an...
View ArticleMTS - how to use cells with identical library name but under different PDKs
Hello,I am trying to setup my MTS bench. For both the technologies, we have custom IP libraries with identical names. Is it possible to assign a different cds.lib for the MTS cells, so that they pick...
View ArticleviaMap in streamout.
It's been many years since Ive had to do a streamout, and I notice there's a "new' option. The streamout log file included warning about using an option called "viaMap". The streamin looks perfect...
View Articlereplace square bus notation brackets with < and >
I imported a Verilog netlist into schematic. All is well, except all nets and pin use square bracket bus notation ,[], instead of <>I have tried using the "replace" function under "edit" menu in...
View Articlewhat is the meaning of iprobe component in analogLib?
recently, I want to measure a basic opamp in virtuoso. My classmates suggest me use the iprobe component to measure it. I read the describetion about iprobe in Spectre document. It says"Current through...
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Layour Passing LVS but failing passing PEX extracting calibre. Anyone know why?
Hello. I'm finding trouble when doing with extracting calibre from my layout. I post screenshots of my situation. I was doing an OR gate circuit layout. It successfully passed nmLVS. But when I was...
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Spikes on my signal
HiI was working on RF Receiver and i finished it but the output data has spikes on it due to using multiplexer at the end." The output was like (00 01 10 11) and i wanted to convert it to pam4 signal...
View ArticleHow to change VIVA zoom time-axis (Shift+ mouse scroll)
Hello,I am using Virtuoso IC6.1.8-64b.500.24, and Spectre 21.1.0.334.isr6. Whenever I plot any waveform on VIVA and try to zoom-in the time-axis using (shift+mouse scroll) it doesn't do anything....
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cannot delete extraction cellview
There is one extraction cellview that I want to delete, but somehow I cannot do this.This is the message from CIW.How should I format the env var CLS_LOCK_HARD_LINKS?envSetVal("??????????"...
View ArticleSTT MTJ Model
I would like to build an STT-MTJ model in cadence .I found a model given in the http://www.spinlib.com/STT_PMA_MTJ.html. model and manual is available. But i am not able to understand the way of...
View ArticleDc level shifter
Hi i have a signal varying from - 0.3 to 0.5 voltsWhat's the simplest way to dc shift it all to positive value all by the same ratioLike 0 to 0.8
View ArticleHow to simulate (equivalent) noise (charge) of CSA?
Hello, I have done this simulation previously when I had only the CSA. Back then, I used noise analysis, found the output-referred noise voltage, integrated it, and then divided it with the Cf. Now I...
View ArticleAlter Device Parameter when Device is in Array
I am attempting to alter a device parameter in a Spectre simulation (19.1.0.237.isr3). In my netlist, I have the following line, for exampleP_A4P0 alter dev=N0<0> param=p_enable value=1When I...
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Noise analysis shows different transfer function compared with AC or XF analysis
I always consider the gain from the noise anlaysis is the same as the transfer function.But it seems that they are defined differently.As can be seen in the picture below.AC and XF analysis show the...
View ArticleIndago waveform is not showing after Design reload
Hi,I am facing the issue where indago waveform goes blank after I reload design. Below are the steps 1. I simulate and open the waveform in indago2. find the RTL issue, fix it and re-run3. reload the...
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Signal doesn't reach full swing (0 -> VDD) in post-layout spectre...
Hi,I'm simulating a digital full-custom design using Spectre (20.1.0.298.isr9) in ADE Assembler (ICADVM20.1-64b.500.21).The layout is DRC and LVS clean. The extraction was done with Cablire (xACT, xACT...
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