replace square bus notation brackets with < and >

I imported a Verilog netlist into schematic. All is well, except all nets and pin  use square bracket bus notation ,[], instead of <>

I have tried using the "replace" function under "edit" menu in schematic but have not figured out the in and out of the character recognition syntax. Some help would be appreciated.

basically, I want to replace out[0], out[1],  etc with out<0> out<1>, etc