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Error while simulating a project on ADE(XL)
Hello. I have recently purchased the license of cadence tools and we have installed tools and configure license file successfully. While running the simulation for a simple CMOS inverter i get the...
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Generating Liberty (.lib) File From Verilog-A Table Model
Hello,I want to create a liberty file for a new technology that I have access to verliog-A table model using Cadence Liberate. I can't find any guidance in the Liberate documents. Is it possible to use...
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Selecting shapes contained in/inside shape
Hi,I am looking for a way to select all shapes contained within another shape.I have a list of candidate shapes and I want to test to see which ones are inside a polygon shape (in this case an annular...
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Double sided spectrum in PSS simulation
Hello,I am curious, If we can plot double sided spectrum (freq axis also having -ve range) in PSS analysis.If so, How to do that ?Thanks in advance
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How to snap different layers to the edges of other layers? (Virtuoso Layout XL)
So I used to work with Tanner L-edit and it had this beautiful mouse snapping, where the mouse would snap at the edges/center/corners of another layer/instance so I could easily draw layers and end...
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Frequency Measurement when clock is constant (veriloga)
Hello All,I am trying to create a model which is dependent on the frequency of the input signal clkA_in3m.I am using the model "Frequency measurements (dg-vams4-8)." as a...
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How to keep attached shapes of a multipart path when chopping the multipart path
Hi,I create a multipart path and some shapes attached to it.However,those attached shapes get lost when I chop the metal of the multipart path.I wonder how to keep those shapes attached to the...
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Disable "copy to cellview" option in ADE Variables
Hi,Is it possible to disable "copy to cellview" option in ADE Variables using Skill or any other way?Thanx
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SPICEIN: How to import mutual inductance K?
Hi,I am using SPICEIN to import a SPICE netlist to a schematic. The SPICE netlist contains resistor, capacitor, inductance and mutal inductance.I am using a deviceMap file.Resistor, capacitor and...
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skipping digital registers in analog extracted simulations
Hallo, I would like to simulate my design after layout. My design consists of a big analog part and a lot of shift registers that are used to configure the analog part.Now I finished the layout of all...
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Regarding cadence virtuoso installation
I am new to Linux and trying to install cadence virtuoso (Base & Hotfix IC618 ) in CentOS 8 system. I wrote the bashrc file as below but was unable to access the virtuoso software. Please somebody...
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Relative path for Ocean script in Maestro
Hello,I have an Ocean script, which I added to my output setup in maestro. When I added the script from a local folder, it got copied to the 'ScriptDir' within the maestro cell view directory. The path...
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How to run encrypted Pspice model in Cadence?
Can anyone please help me on how to run encrypted pspice model in cadence?
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Setting up a jitter simulation for Ring Oscillator
Hi,I am designing a programmable CMOS ring oscillator in Virtuoso ICADV12.3-64b environment.By using different digital control settings, I can choose the odd number of inverters in the ring...
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[Virtuoso layout XL] How to switch between quick align User Spacing and quick...
So currently I have to do A>F3>use mouse to select No Spacing or User Spacing and then align, but I switch between them pretty often and it looks like if there was a bindkey for switching them it...
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DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction
Hi All,I'm simulating a post layout r_c and r_c_cc extraction of a transmitter circuit for transient simulation using config view, The problem is when simulation starts it checks for the "Trying...
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Could anyone explain this sampled noise simulation result
Hi, I'm learning sampled circuit noise simulaton, pss+pnoise, start with the simplest S/H circuit.- Simulator, Spectre 19.1- TestBench (fig1), a switch-capacitor S/H circuit, as switch sampling...
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Navigator net highlight/probe and navigator net 'XL status' issue
(1) When selecting a net from navigator or probing that net, it does not highlight the all the shapes that is connected to the net(the ones that are 1-2 levels below). I tried tinkering around with...
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ADE Assembler - calcVal + Monte Carlo + Reusing Trim Codes in new MC for...
Hi,I am simulating a calibrated circuit in ADE Assembler. I have Virtuoso version ICADVM18.1-64b.500.13. Simulation Method:I run two tests for each Monte Carlo sample--one for finding the right...
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Weird behavior on "save" statements.
I have the following analyses defined.tran tran stop=10n infonames=[dcnode] infotimes=[0.1n 9.9n 30.9n] infotime_pair=no save=selecteddcnode info what=oppoint where=rawfile save=selectedMy save...
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