Generating Liberty (.lib) File From Verilog-A Table Model

Hello,

I want to create a liberty file for a new technology that I have access to verliog-A table model using Cadence Liberate. I can't find any guidance in the Liberate documents. Is it possible to use the Verilog-A model instead of the Spice model to create a liberty file using Cadence Liberate? Can anyone help me with how I can do that?

Many Thanks