Hallo,
I would like to simulate my design after layout. My design consists of a big analog part and a lot of shift registers that are used to configure the analog part.
Now I finished the layout of all components including analog and registers together. When performing analog extracted using quantus of the top level I can not longer configure the value of the registers since I can no longer set the cell view to veriloga in the config. Therefore I can only simulate the system with registers have a value of zero.
Is there is a way to generated an analog extracted view without flattening the registers as well.
Thanks and regards
Mohammad