design/global variable expression
Hi,I would like to write the design/global variable as: [1:1:10]*(1-x), x is another variable, it is supposed as a vector times some other expression, but assembler reports the syntax error.Is there...
View ArticleExport netlist for cell selected
Hello Guys,Can anyone explain ..how we can export a netlist for a cell..I have made a lib and cell string box with browse button..i want that when user selects any cell from lib..it automatically...
View ArticleServer processor selection - any difference in performance and features (AMD...
Hi all,we are about to get a new server for our ASIC development.We have to decide between AMD-Epyc-32cores (cheaper) and Intel-Xeon-24cores (more expensive).We are wondering if there would be any...
View ArticleLiberate AMS: Observation window for async OTP memory
Hello,I need to characterize and generate .lib file for async OTP memory. In this case, what should be the observation window size?My understanding is, that observation window needs to be wider than...
View ArticleLiberate AMS GUI: arc present in log file, but not generated in .lib file
Liberate AMS GUI: arc present in log file, but not generated in .lib fileHello,I am using dynamic arc generation, Liberate AMS GUI.I have problem that my two arcs, which are defined in Define Arcs tab...
View ArticleParameterizable Voltage Controlled Oscillator Model
Dear Community,I want to simulate an analog, custom PLL circuit (trans, ac, hb using ADE XL). For this I need to implement a behavioral VCO model, easy task in ADS so Cadence should of course offer a...
View ArticleCan tests in Assembler use different config views?
Is it possible to use difference views for a cell in different tests?There's an RMB option to add config sweep to global variable. When I tried to copy that global variable's name and value to local...
View ArticleHow to see parents cell of a layout ?
In Tanner EDA tool there was a simple 'Parents' options in the library navigator, to see if my current layout has been used in another layout. But in cadence I think it gets a little complicated. I...
View ArticleCopy of group with MPP results in flattened MPP
I have a similar problem as described in this thread: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/36786/synchronous-copy-of-group-with-mpp-results-in-flattened-mppIf I...
View ArticlePlotting a function on Cadence calculator that requires the temperature read...
Hello,I am dealing with temperature to frequency sensor design.I have simulated the output frequency as a function of temperature in the range from -40 to 85I need to calculate and plot the sensor...
View ArticleHow to get phase noise from noise summary at paticular frequency?
Hi guys,I'd like to correlated Phase Niose curve with noise summary after pss. I decide to pick 10kHz as a test point, but I find that the logarithmic value of total summarized noise printed in noise...
View ArticleSNR for Sigma Delta Modulator: Questions on Filter and DC Input
Hi,I'm designing a Sigma Delta Modulator and I'd like to calculate its SNR (or more accurately, SINAD).I reviewed the spectrum assistant AN, which was quite helpful, but I still don't have answers to...
View ArticleFormat for montecarlo sweep in a *.scs file included with ADE Assembler
mctrans montecarlo numruns=10 variations=mismatch seed=1 json=yes savemismatchparams=yes \\ <-----UNEXPECTED END OF LINE mismatchscalarfile="*/*/mis_sc_file.txt" \\...
View Articlecross function deficiency
I used to work at an IC design company that had it's own analog simulator and corresponding scripting language and I am now at another company using Cadence Spectre and Ocean scripting (I'll bite my...
View ArticleHow to formulate the "best fit line" in Vertuoso calculator
Hello,I am using Cadence Virtuoso version IC6.1.8-64b.500.6Kindly I would like to ask you how can I formulate the best fit line function in the cadence calculator for the purpose of simulating the...
View ArticleHow to make auto via feature in cadence avoid slot layers since it causes DRC...
Even though Prevent DRC violations is turned on which does work for metal layers and other vias, but does not work for slot layers?
View ArticleMeasurement across Corners/Sweeps/All in ADE Assembler
Hello,I am using Cadence Virtuoso version IC6.1.8-64b.500.6I am running some calculations at the result of specific corner. for example, I am calculating the average current at the output of a resistor...
View ArticleHow to add stop layers to annotation browser?
Just like how we can add stop layers for Mark Nets, can we do something similar to annotation browser?
View ArticleRe-running a particular iteration of the montecarlo sims
This question was asked before here.I ran a montecarlo simulation, with seed=1 and 100 iterations. I now want to run a more detailed simulation on iteration 77. Is there a way to do it? I tried using...
View ArticleMeasuring XStream performance in Virtuoso
Hi. I'm studying Virtuoso and circuit design.I have a question about XStream performance.When I executed "stream in" on library A, it took 800 seconds. After finishing stream in, i repeated same...
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