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parasitic extraction on "updated" schematics
Hi, I have a question on how cadence handles extracted netlists during simulationIf I have a schematic/layout that is LVS clean, I can of course use that RCE file to simulate with extracted...
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preparation for verifying large blocks
Hi expert,I will go to verification(dc) for upper hierarchy soon.What should I be careful about convergence? a) node set b) dcOp: use the prepared file, it was solved Op with lower gmin. c) mitigation...
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Model parameters clarity
Hello, I am a novice/student and have been using virtuoso since only about 3 months for designing DAC and current mirror biasing circuits. I have always used gm/Id methodology. Here, I would reference...
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APS++ for AMS mode (NOT in spectre mode)
Dear All,I am running a transient simulation in AMS mode.The blocks are written in Verilog and they have real variables too.Is it possible to enable APS++ for this simulation ?Kind Regrads,
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Unable to plot from ADE Assembler results tab
IC6.1.8.500-170,Hi all, I've been running some simulations using calcVal and I'm unable to plot the output waveforms when I right click select them. The CIW prompts:"rdbLoadResults("fnxSession1"...
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Edit schematic with python
I'm doing an optimization project. First, I create a simple schematic containing several resistors and capacitors with virtuoso. Then, I need to change the resistance or capacity of instances and...
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Is it possible to also save phase information for the gain transfer function...
Hi, I was wondering if it is possible to get plots for the phase of the transfer function in noise analysis like in AC analysis without the need to run AC analysis. It would be really helpful and save...
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Need a solution to build pre-computed look-up table manually
Hello.Recently, I read 'Systematic Design of Analog CMOS Circuits', which describes how to apply pre-computed look-up table.Look-up table is 4-D DCOp table e.g. ID(L, VGS, VDS, VSB) gm(L, VGS, VDS,...
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Repeating vector files
Hallo,I am simulating a circuit with one input vector file, but I want the same vector to be repeated for the whole time of simulation with no stop. Is there a way to make a vector file repeat itself...
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check and save schematic, there's a warning I don't know where it comes
I copy a schematic from old library (read-only) to new library so that I can edit. After I just copied, and no modification just check and save,this warning shows:INFO (SCH-1170): Extracting...
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Schematic Grid Dot Size
Hi there,For my work I often end up displaying a higher-resolution VNC window on a lower-resolution screen, like my laptop window. As a result of this, the schematic grid dots can become pretty hard to...
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ADE Assembler: variable values with leading zeros interpreted as octal in...
Hi! We recently switched to ICADVM20.1 and started to get weird results in many old testbenches. After a close lookup, it turns out that all the variables with values starting with zero ("0") are being...
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create a copy of device library, some parameters' limitCheck failed....
I am doing the porting one project schematic from PDK1 to PDK2 (both GF foundry PDK). In order to keep the original wire connection, I uses the symbols of the element devices from PDK1 as reference...
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[LVS Error] Missing ME1_PSUB via
I'm trying to create the right layout for an inverter using UMC's 180nm technology library and I get an LVS error because I can not make the body connection for the nmos. The connection requires an...
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passing variable number of params in spectre subckt call?
I'm trying to create a custom parasitic wrapper for a transistor. Something very much like the example from the Spectre reference manual for inline subcircuits.Here's an example:inline subckt...
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some questions after using abConvertComponentParams.il to do schematic porting
Hi I am using abConverComponetParams.il (SCCS Info: @(#) abConvertComponentParams.il 05/23/05.12:00:00 1.7) to do the schematic porting, it is very powerful. But there are some points I want to know...
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Cadence Abstract DLNOLK : Failed to get exclusive lock
Hi All,I've been using Abstract for sometime to generate cell abstract views. However recently ran into this issue when I tried to specify the logical views to the cells in a library (TSPC_R_ABS) using...
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How can I generate this repeating pulse?
I want to generate a pulse that repeats this voltage pulse at cadence virtuoso schematic. (Fig.1) (Fig.1 I want to generate a pulse that repeats this voltage...
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How to remove highlight after DRC check in IC Layout design
Hello,I would like to ask about how to remove the highlights created on the layout after DRC checking in Cadence Virtuoso.Thank youRegards
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