Hello.
Recently, I read 'Systematic Design of Analog CMOS Circuits', which describes how to apply pre-computed look-up table.
Look-up table is 4-D DCOp table e.g. ID(L, VGS, VDS, VSB) gm(L, VGS, VDS, VSB)...
The book provided look-up table generation tool, and that requires Spectre MATLAB toolbox.
Because I access Cadence through Unix server, and I cannot use MATLAB on the server, I cannot apply that method, so I decided to make look-up table manually.
The method I chose is that...
1. Turn on ADE-L, and run multiple DC parametric analyses at once.
2. Export them as .csv
3. Organize them manually.
(I am a cadence beginner...)
There are many problems I encounter, but the main is that...
Parametric Analyses suddenly comet to a halt without error.
No error message. No freezing. Just halt(pause and continue does not work).
I use multiple duplicated schematics to separate directories.
The fundamental problem which cannot be fixed is that I cannot run MATLAB on the server.
So, I should run simulations and export the results.
1. Is there any solution to fix random halt?
2. Is there a better solution for me?
Thank you!