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Improve VCO Verilog-A model accuracy
Hi everyone,for the needs of a Verilog-A sqaure wave VCO model including jitter (white_noise, to start),I'm racking my brain on a way to encode it without setting 1fs fixed points to improve accuracy...
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Voltus-Fi PDB File Location
I have been able to successfully run Spectre EMIR simulations and view the results in Voltus-Fi. I am running from ADE and the default sim directory is <simdir>/config/. I saved a copy of the...
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Verilog-A white_noise function returns 0 in transient noise simulation
Hi everyone,How come the white_noise function returns 0 in transient noise simulation?As a matter of fact, for a reason I ignore, depending on the whether outside probably, sometimes it works,...
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HISIM-HV models
Trying Simulation HISIM-HV 2.40; in virtuoso ADE-L environment, it does not seem to read the level =73 or 75 model number. Two questions1) what is the appropriate level number 2) where do I get this...
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noise sim always report 0% of Total
IC6.1.8-64b.500.11Have a simple RC network with the resistor of polyR type. Run a noise simulation to verify the KT/C noise.Don't know why "% of Total" column always report 0.If you see the other...
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Working model for MDL language - A query
Hi,with reference to Virtuoso IC6.1.8-64b.500.13I've recently come across the Measurement Description Language, although I gather this has been available r for many years now.The possibility of...
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Getting Flat Outputs while implementing a 6 Bit Flash ADC using VerilogA.
Hi,I am trying to model a 6 Bit Flash ADC using VerilogA.Here is the code : `include "constants.vams"`include "disciplines.vams"module ADC(vout, vclk,vin);output [5:0] vout;electrical [5:0] vout;input...
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Post Layout simulation for multi-finger transistors
Hello,In the post layout simulation for a transistors built of number of segments/fingers, the simulated current in cadence shows only the current per one segment, then I have to multiply it myself to...
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Using FinFETs in OrCAD Capture
Dear Andrew,Happy to see your reply on blogs and forum. Today I have started to work on FinFETs in Cadence OrCAD capture. I could not find the finfet in the library.Am very new to cadence and please...
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Verilog-AMS Simulation speed issue while using $table_model for reading from...
Dear All,I was using $table_model to read data from a file in each event for 5 times.But, now I need to use $table_model to read data from a file in each event for 25 times.This significantly increases...
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How can I fix the error in my simulation?
I simulated the circuit of Figure 1. Figure 1And, I imported the moded card of NMOS, and its text is as follows.** Predictive Technology Model Beta Version* 180nm NMOS SPICE Parametersv (normal...
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Restrict ICPR SGE Job to only run 1 simulation point (ADE Assembler)
Hi,I would like to restrict ICPR to launch a new job for each simulation point - I tried following this:...
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Layout offgrid problem
Hello,In the middle of my layout design I started to receive a new error of "OFFGRID". I have read some advices from net about changing the minor and major spaces from Option > Display, however it...
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How to pass a real array as an input argument to a function in Verilog (in...
Dear All,I need to write a function (see below) in verilog for AMS transient simulation.I could pass a real value "delta_t" as an input argument to the function but not the a real array...
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Can I use a variable as interpolation point in the value function?
HiI'm trying to setup the interpolation point of the value function from a variable, I've tried this but it doesn't work:any idea on how I can achieve this?Thanks
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Update W/L number in instance property, but resistor "r "value isn't change...
Hi everyoneI am just using the PDK from the foundry. I just followed its cdslib userguide. when I launch the virtuoso IC618 and create schematic. I add one instance of resistor using "add instance"....
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How can I solve the "ERROR (VIVA-9000)" ?
Hi all,We got the "ERROR (VIVA-9000)" in Monte Carlo simulation. ERROR (VIVA-9000):No image saved: Possible reasons could be that none of the windowsor subwindows are visible or are non-empty.What's...
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ADE Explorer - Spec Pass/Fail
Hi,Is it possible to put the 'temperature' variable that exists inside the Corners as a variable inside the "Spec" column during output setups? For example, I want to normalize my outputs with respect...
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recreate"?">Any bindkey to run "netlist -> recreate"?
Hi, I am wondering if there is any bindkey which is able to define "netlist -> recreate" in assembler and/or schematic view?My virtuoso version is IC6.1.8-64b 500.2. Thanks for your attention. BR
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calcVal failure: Job log says some outputs used by Calcval have failed, but...
Hi,I have a ran into a very frustrating problem with calcVal.I have these tests selected:AC_IF_BIST (test 0) uses expressions from AC_CALIB_IF_BIST (test 1) and config_schematic_schematic_ac (test...
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