Getting Flat Outputs while implementing a 6 Bit Flash ADC using VerilogA.

Hi,

I am trying to model a 6 Bit Flash ADC using VerilogA.

Here is the code : 

`include "constants.vams"
`include "disciplines.vams"

module ADC(vout, vclk,vin);
output [5:0] vout;
electrical [5:0] vout;
input vclk;
electrical vclk;
input vin;
electrical vin;
real vdout[0:5];
real trise = 1;
real tfall = 1;
real tdel = 1;

real vth = 0.9;
real samp;
integer i,vd;
real lsb = 0.015;

analog begin
@(cross(V(vclk) - vth,+1)) samp = V(vin);
vd = (samp - 1.8 )/ lsb;
$display ("The value of samp is %g",samp);
$display ("The value of vd is %g",vd);
$display ("The value of time is %g",$abstime);

for (i=0; i < 6 ; i=i+1 ) begin
vdout[i] = vd%2;
vd=vd/2;
$display ("Value of vdout is %g", vdout[i]);
end

V(vout[0]) <+ transition(vdout[0],tdel,trise,tfall );
V(vout[1]) <+ transition(vdout[1],tdel,trise,tfall );
V(vout[2]) <+ transition(vdout[2],tdel,trise,tfall );
V(vout[3]) <+ transition(vdout[3],tdel,trise,tfall );
V(vout[4]) <+ transition(vdout[4],tdel,trise,tfall );
V(vout[5]) <+ transition(vdout[5],tdel,trise,tfall );
end

endmodule

In output i am getting all the flat lines resting at 0 when i am giving a 100ns period to the applied clock i.e vclk, when i print the conversion values i am getting vdout as per my Vin ( kept 2.1 ) analog voltage in my run log but the waveform still shows it 0 . Can anyone tell me what is wrong with the code or if anyone has a working model of Flash ADC i would be thankful.

Regards,

Kulmani