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Getting the wellpin in lef using abstract
Hello,so I am trying to get the pwell information in the lef but in the layout I don't have pwell drawing but just the label.I looked into IC618_AG_RAK document but it is not working for me.In the...
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How can I create this switch at cadence virtuoso?
I want to create a switch like Figure 1. (Figure 1. I want to create a switch like this switch.)I think if I use sp3tswitch, I can create a switch like...
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How can I add suffix for subcircuit with $ in cdl netlist
Hi, Cadence FamilyI have created a pcell subcircuit with editable CDF parameter named "suffix".Then cdl netlist will be " X1 pin1 pin2 cellName " in default.Is there possible to add suffix for...
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Plotting A Line Graph Across Design Points in ACTIMES Tran
Hello.I am doing a transient simulation with actimes....at a number of points in the transient simulation I am doing a small signal real and imaginary impedance measurement.When I come to plot this,...
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How to get a value as an output to an expression
I'm using the above expression to get the dc loop Gain, and i expect the return of this expression to be a value. But what I get is again a single point plot as shown below:What should I do to get a...
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Ocean script for printing parametric sweep dcOp
Hello,I need to simulate multiple MOSFET parameters (gm, gmb, cgg, cdd, etc) on different bias conditions and export the output in a custom table in a text file.I suppose the best way to do this is by...
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copy only one layer in order to connect nets by name
I need to copy only one layer I cannot see how to do this. Using nv I can show one layer but when I go to select it selects even what is on other layers.Then if I can find a way to do this, I will...
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Question on Sampled (JItter) PNoise analysis
Hi everyone,I am doing noise analysis on a track and hold circuit (a switch cap followed by a 16GHz 3dB-BW opamp model) with PSS+ Pnoise. The tool version I am using is ICADVM20.1-64b.The switch is...
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Simulate accumulted jitter spectral density vs. unit jitter spectral density...
Hi,I can't figure out the new terminology of Cadence about the phase noise. Could you please give me a help?I wan't to simulate the phase noise of a VCO, but I'm not sure of what I'm simulating. And...
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Connect bus to GND via resistors for simulation
I am new to Cadence. I have to simulate a design which has two outputs "COUNT" and "SAFF" each with 7 and 21 bits respectively. I want to connect a 1 kΩ load resistor to each and then to ground. I have...
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DC operation point only print limited results
Hello everyone,I am using Cadence 6.1.7-64b. When I run the dc simulation and want to check the dc operating point of the transistor. Only limited number of results are printed as shown below: I would...
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ADE Assembler release license
Hi, is there a way to release an ADE Assembler license once I'm done using it?I closed all cells and that license is still used.I'm using virtuoso IC6.1.8-64b.500.15
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Generating real random number in AMS
Dear All,Is there any way we can generate real random number with a given mean and sigma in AMS (without any any analog block) ?Kind Regards,
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Defining supply voltage (and basic connect rules) for digital block for runams
Hi,I am trying to create a commandline simulation of a mixed-mode testbench (config view). I am strugling quite some with trying to define the supply voltage etc. for the digital part?I've tried...
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How can I probe the temp value in tran simulation ?
Hi all,Although I got how to run simulation with dynamic param from posted, I could not find the how to probe the temp value in tran.regards,Ichiro-how to set dynamic...
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Issues in accuracy of clock generation in Verilog-AMS with white noise jitter
Dear All,I am trying to generate a jittery clock with white noise (normal distribution) jitter of zero mean and 10m UI sigma or standard deviation. To check the clock generation is proper, I also...
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Variable net name in Virtuoso
HiIs there any way to set the net name in virtuoso as a variable and control it through ADE?
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Setting for setting the analog stimuli
Hi All,is there a way to set the value of multiple bits inside the Stimuli setup window in one go.for example in the below snapshot i wish to set all the series<1> to series<7> to DC...
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How to combine two procedure syntax and use by bindkey layer?
Hi! All:I have question about syntax use,And thru the toggle Bindkey combine two procedure syntax implement I wanna to I think toggle keyboard "1" is setMetal1LayerVisible(), and toggle keyboard "Alt...
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Stop an area of a schematic being netlisted.
It would be extremely useful when debugging simulations to quick stop parts of a schematic being netlisted.Im thinking some kind of layer or bounding box.Current workaround = is saving hacked versions...
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