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Stretching multiple layout wires at once
I have been trying to stretch multiple metal 1 wires (pathSeg). (Cadence 6.18) I've tried selecting them all then pressing s, only they all just move instead of stretching. Reading a bit on here I then...
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HB Analysis on PLL
Dear Cadence SpectreRF Experts:I am running HB analysis on a PLL. PLL reference is 20MHz and its output is 240MHz. Its VCO operates at 480MHz and there is a fixed divide-by-2 at the VCO output and a...
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dynamic stop time in transient analysis
Hallo,Is there anyway to make the transient analysis stop on a dynamic time, in other words can I set the simulation to stop when a signal or specific temperature is reached? I have to run my analysis...
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No such feature exists. error from lmutil lmdiag command
Some of the 111 license file entries are giving me "No such feature exists." when I run lmutil lmdiag command. Some of the 111 licenses are fine. All the license entries are from the same license...
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DSPF cellview in Hierarchy Editor will be always netlisted with "subcircuit"...
Hello everybody,I've noticed, that I can select a "DSPF" cellview in the hierarchy editor a for a cell. Unfortunately the netlister does not recognize the model name.The subcircuit definition in the...
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How to move symbol origin for only SOME instances
About symbol origins in cadence virtuoso,I have an old symbol with a messed up origin. It is inconvenient when placing a new instance. However, many schematics use the symbol so if I change the origin...
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Controlling the displayed number of floating decimals in the DC operating point
Hello to everybody,I have a simple doubt. When I annotate the DC operating point in the schematic, the number of decimals displayed is very high (e.g. Ids = 100.1234567891234 nA). How could I modify...
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Dynamic tolerance with Spectre X?
Is it possible to dynamically alter the spectre X tolerance in a transient sim?For APS this can be done by changing the "errpreset" variable between conservative/moderate/liberal.Spectre X accuracy...
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Netlisting flowchart postFunc called multiple times with Assembler & ICRP job...
I'm attempting to insert a custom function in the netlist flowchart that will modify the netlist after creation.This works in most cases. I'm netlisting/running from ADE Assembler.If I just netlist by...
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Running AMS netlist from unix terminal
Dear All,I have created the AMS netlist in ADE. It generates the netlist file as .completeDesignInfo.ckt.I ran in the unix terminal, from which I have fired virtuoso, as below but I get the permission...
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What is the difference between pmos, pmoshiv, pmos3, and pmostie in Cadence...
Hello,I am using gpdk018 to simulate my design and found that there are three or four different types of mosfet.Could you let me know that what is the difference between pmos, pmoshiv, pmos3, and...
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importing spice model into cadence virtuoso ic design
Hello,I need to use adg1436 spice model in my simulation, I tried to add a new cell with cell view of type spice, but I get tens of parsing errors when I try to save it.Can you please explain for me...
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Print high-resolution layout image in cadence virtuoso
Hello gentlemen,I apologize for the inconvenience or inappropriate writing, because it is my first time to writein the community,I work on a project and I want to get high resolution image from the...
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What is meant by "device parameterization" in relation to...
Hi,We are exploring the "ignoreDesignChangesDuringRun" variable for the ICRP mode, and was trying to understand what the specified limitation in the user guide is referering to?Quote:When the ADE...
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how to temporary short together bus in schematic for lvs
I have a pmos instance PM70<11:0> the sources are connected to vdd and the gates and drains are all connected together now the gates and sources are just floating but connected in to a single...
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= 0.08 um"?">DRC DIVA. How can I solve this marker text: "Space to three adjacent Contacts...
I am designing a simple inverter to test the gpdk045 library, and when performing the DCR with DIVA, this appears: "Space to three adjacent Contacts (<0.10um apart)> = 0.08 um"? .I generated the...
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Automated way for creating custom layout cell view for polygon shapes
Hi All I need some advice on creating a layout cell view that has a 45 deg rotated square for multiple conductor layers in the PDK.Can anyone please suggest an automated way to generate this shape for...
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Virtuoso Spice In Device Map property is not honored
Hello,I have a spice netlist with multiple different resistors and I want to import it into Virtuoso by Spice-In from CIW (File > Import >Spice). A sample of my netlist is shown below:R1 2 VDDESD...
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Spectre terminated due to fatal error
Hello Sir,Whenever I try to simulate any verilogA code the same error keeps on coming. The log file is attached herewithTime for Elaboration: CPU = 279.958 ms, elapsed = 603.707 ms.Time accumulated:...
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Layout XL generating MOS without source contacts.
I am generating a layout using Connectivity>Generate>All_from_source using Cadence 6.18This works very well only most of the sources do not have metal contacts and even when I instance a new nmos...
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