Clik here to view.
ADE XL simluation stuck
Hallo everyone,I'm running a simulation in ADE XL with 3584 point sweeps, it is stuck somehow at 3583....This happens sometimes. After I need rerun the simulation sometimes it doesn't stuck anymore....
View ArticleClik here to view.
can analog pad be used as power pad (power is ac sinosuid)
hello.I am working on a project TSMC 65nm where I am using ac sinosuid as a power source (No Dc is being used)So can I use analog pad as a power pad having ac sinosuid signal.and will it require a Esd...
View ArticleClik here to view.
ddt() at a certain timestep in Verilog-A
Hi,ifelectrical [0:n] x_node;electrical [0:n] d;parameter real n=5;real a=1e-9;genvar i;//... for(i=0; i<n; i=i+1) begin V(d[i])<+ a*ddt(V(x_node[i]));end//...Is it possible to find V(d[i])...
View ArticleClik here to view.
license to run spectre electro-thermal demo
HI i am tring to run demo from spectre/examples/SpectreThermalAnalysis/powerMOSusing spectre -64 ++aps input.scshowever, error message indicates license is not avaliable. btw, standalone spectre is...
View ArticleClik here to view.
How to update schematic without layout
Hello,Do I have any best way to update schematic without update layout?This is the situation below,I received the new schematic data from our customers, and I want to update to schematic to my working...
View ArticleClik here to view.
Automatically Export Spectre AMS-Output-Data
Hello,I am doing some transient mixed-signal simulations with Spectre AMS in the ADE environment, which works like intended. However, I would like to automatically export the output data which is in...
View ArticleClik here to view.
Is there a way to exclude vias when highlighting nets using Net Tracer on...
I observe that when highlighting nets with many vias the Net Tracer will get very slow.So, I was thinking of excluding vias when using Net Tracer and see if it is faster.Is this possible?
View ArticleClik here to view.
Update global variables from active setup to run plan
Hi,I have a maestro view which is mainly used by another designer. He sometimes updates the maestro view with more variables placed in the corners, or just adds more global variables in general.This,...
View ArticleClik here to view.
compare two netlists
Hi, I need to compare two netlists frequently, one is old netlist, one is new netlist. Suppose only several updates have been done in the design, meaning 99% of netlists should be the same.But when i...
View ArticleClik here to view.
Using variables with spectrumMeas
Hello -Variables work with the spectrumMeas function except for the "number of samples" entry. It requires an actual integer number. Is there a work around?For example, this...
View ArticleClik here to view.
VerilogA $limit with spectre
Dear Cadence community,is there any roadmap to support in future with Spectre the full functionality of $limit() function in Verilog-A? Is there any alternative to that?Thank you.
View ArticleClik here to view.
import a Spice Model in a schematic
Hello,I would like to import a model which is written in Spice. In the end, I want a simple symbol which contains this model and which i could place in my other schematics.The model I want to include...
View ArticleClik here to view.
"the following branches form a loop of rigid branches"
Hello all,I'm designing an xpair for a sinusoidal oscillator, and while doing an ac analysis, the following error appears:The circuit is as follows:From the error, it is plain that the AC source V1 is...
View ArticleClik here to view.
Resistor Noise Calculation using FFT and Noise Analysis is different
Hello,I am doing a simple simulation for a circuit noise and found that the FFT spectral measurement gives different results compared to noise simulation. This test bench shows the difference:The...
View ArticleClik here to view.
Connecting PMOS body to VSS! in Layout XL
Hi, I would like to intentionally connect the body terminal of PMOS to VSS!. Generally for drawing PMOS with body connected to VDD! , Oxide-poly layer is placed in an NWELL which is then connected to...
View ArticleClik here to view.
Generating .lib file for synthesis using Genus from transistor level cells...
I am trying to create a standard cell library by drawing the transistor level schematics in Virtuoso.I want to be able to use these cells for synthesis using Genus.I understand that Genus requires a...
View ArticleClik here to view.
How to plot difference of simulation result from Monte carlo and standard...
We can run a standard simulation and get curve A. We also can run n point Monte carlo simulation and get curve B1~Bn. I want to plot the difference between curve B1~Bn and curve A, that is B1-A, B2-A,...
View ArticleClik here to view.
Clik here to view.
Print high-resolution layout image in cadence virtuoso
Hello gentlemen,I apologize for the inconvenience or inappropriate writing, because it is my first time to writein the community,I work on a project and I want to get high resolution image from the...
View ArticleClik here to view.
Bad value "primary" for parameter - Characterising cells using Liberate
I have designed a few cells in Virtuoso and I have the post layout (spice) netlists. I want to characterize them as a .lib file so that I can port it into Genus for Synthesis runs.(...
View Article