I have designed a few cells in Virtuoso and I have the post layout (spice) netlists. I want to characterize them as a .lib file so that I can port it into Genus for Synthesis runs.
( https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48008/generating-lib-file-for-synthesis-using-genus-from-transistor-level-cells-using-virtuoso/1375267#1375267 is a backstory to this )
I read the user guides for Liberate, and I setup my .tcl files as follows
.
|-- char.log
|-- netlist
| |-- AND2X1.sp
| |-- INVX1.sp
| |-- NAND2X1.sp
| |-- NOR2X1.sp
| |-- OR2X1.sp
| |-- XNOR2X1.sp
| `-- XOR2X1.sp
|-- tcl
| |-- char.tcl
| `-- settings.tcl
`-- template
`-- template.tcl
the .tcl files are as follows
--tcl/char.tcl--
set SRC_DIR [pwd]
#set SRC_DIR ${ROOT_DIR}/liberate_env
set RUN_DIR ${SRC_DIR}/run
set PROCESS tt
set VDD_VALUE 0.3
set TEMP 25
set LIB lowpower
set SETTINGS_FILE ${SRC_DIR}/tcl/settings.tcl
set TEMPLATE_FILE ${SRC_DIR}/template/template.tcl
set CELLS_FILE ${SRC_DIR}/cells.tcl
set MODEL_INCLUDE_FILE ${SRC_DIR}/models/spectre/include_${PROCESS}
set NETLIST_DIR ${SRC_DIR}/netlist
set USERDATA ${SRC_DIR}/userdata/userdata.lib
set THREAD 2
set CLIENTS 4
set MEM 1024 ;# request 1G per thread
source ${SETTINGS_FILE}
source ${TEMPLATE_FILE}
source ${CELLS_FILE}
set_operating_condition -voltage ${VDD_VALUE} -temp ${TEMP}
set_var extsim_model_include ${MODEL_INCLUDE_FILE}
define leafcell -type nmos -pin_position {0 1 2 3} \
{ N_18_MM }
define_leafcell -type pmos -pin_posiiton {0 1 2 3} \
{ P_18_MM }
set spicefiles {}
foreach cell ${cells} {
lappend spicefiles ${NETLIST-DIR}/${cell}.sp
}
read_spice -format spectre "${NETLIST_DIR} ${spicefiles}"
char_library -extsim spectre -cells $cells
write_ldb -overwrite ${RUN_DIR}/ldb/${LIBNAME}.ldb
write_library \
-driver_waveform \
-user_data ${USERDATA} \
-rename -filename ${RUN_DIR}/lib/${LIBNAME}.lib \
${LIBNAME}
--tcl/setting.tcl--
set_var extsim_cmd_option "+aps +spice –mt +liberate +rcopt=2"
set_var extsim_deck_header "simulator lang=spectre Opt1 options reltol=1e-4 simulator lang=spice"
set_var extsim_option "redefinedparams=ignore hier_ambiguity=lower limit=delta"
set_var extsim_leakage_option "redefinedparams=ignore hier_ambiguity=lower limit=delta"
set_var ski_enable 1
set_var ski_clean_mode 1
set_var ski_compatibility_mode 1
set_var parse_auto_define_leafcell set_var
set_var tmpdir /dev/shm
set_var predriver_waveform 2
set_var min_capacitance_for_outputs 1
set_var force_condition 4
set_var no_change_mode 1
set_var conditional_mpw 0
set_var leakage_float_internal_supply 0
set_var reset_negative_leakage_power 1
set_var voltage_map 1
set_var pin_based_power 0
set_var power_multi_output_binning_mode 1
set_var power_subtract_leakage 4
set_var subtract_hidden_power 2
set_var subtract_hidden_power_use_default 3
--template/template.tcl--
set_vdd –type primary vdd VDD_VALUE
set_gnd –type primary gnd 0
set_gnd –no_model gnd 0
set_var slew_lower_rise 0.1
set_var slew_lower_fall 0.1
set_var slew_upper_rise 0.9
set_var slew_upper_fall 0.9
set_var measure_slew_lower_rise 0.1
set_var measure_slew_lower_fall 0.1
set_var measure_slew_upper_rise 0.9
set_var measure_slew_upper_fall 0.9
set_var delay_inp_rise 0.1
set_var delay_inp_fall 0.1
set_var delay_out_rise 0.1
set_var delay_out_fall 0.1
set cells {
INVX1
AND2X1
OR2X1
NAND2X1
NOR2X1
XOR2X1
XNOR2X1
}
if {[ALAPI_active_cell "INVX1"]} {
define_cell \
-input { in } \
-output { out } \
-pinlist { in out } \
AND2X1
}
if {[ALAPI_active_cell "AND2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
if {[ALAPI_active_cell "OR2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
if {[ALAPI_active_cell "NAND2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
if {[ALAPI_active_cell "NOR2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
if {[ALAPI_active_cell "XOR2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
if {[ALAPI_active_cell "XNOR2X1"]} {
define_cell \
-input { a b } \
-output { y } \
-pinlist { a b y } \
AND2X1
}
Here are the logs when I pass char.tcl to liberate as a command line arguement
--char.log--
$ liberate ../liberate/tcl/char.tcl | & tee char.log
ROOT_DIR = /home/installs/LIBERATE192
exepath = /home/installs/LIBERATE192/tools/bin
Host : cad19 x86_64 Linux 2.6.32-696.el6.x86_64
LIBERATE Library Characterization Platform (x86_64)
Release dev, compiled by vficcm on Tue Sep 10 06:33:00 PDT 2019
********************************************************************
* Copyright (c) Cadence Design Systems, Inc. 2006 - 2021. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it, *
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
********************************************************************
Copyright notices for Open Source and Third Party Tools used by this
software can be viewed at <cds_inst_dir>/doc/liberate/thirdpartyinfo/Notices.txt
LIBERATE started on cad19 at Mon May 10 22:04:13 2021
Command line arguments: '../liberate/tcl/char.tcl'.
ALTOSHOME set to '/home/installs/LIBERATE192'.
Server ID : *hidden*
LIBERATE parameter "extsim_cmd_option" set to "+aps +spice âmt +liberate +rcopt=2"
LIBERATE parameter "extsim_deck_header" set to "simulator lang=spectre Opt1 options reltol=1e-4 simulator lang=spice"
LIBERATE parameter "extsim_option" set to "redefinedparams=ignore hier_ambiguity=lower limit=delta"
LIBERATE parameter "extsim_leakage_option" set to "redefinedparams=ignore hier_ambiguity=lower limit=delta"
LIBERATE parameter "ski_enable" set to "1"
LIBERATE parameter "ski_clean_mode" set to "1"
LIBERATE parameter "ski_compatibility_mode" set to "1"
WARNING (LIB-40): (set_var): Ignored the invalid value 'set_var' specified for 'parse_auto_define_leafcell'. It should be set to an integer in range 0..2.
LIBERATE parameter "tmpdir" set to "/dev/shm"
LIBERATE parameter "predriver_waveform" set to "2"
LIBERATE parameter "min_capacitance_for_outputs" set to "1"
LIBERATE parameter "force_condition" set to "4"
WARNING (LIB-42): (get_var): Ignoring undefined variable 'no_change_mode'.
LIBERATE parameter "no_change_mode" set to "<undefined>"
LIBERATE parameter "conditional_mpw" set to "0"
LIBERATE parameter "leakage_float_internal_supply" set to "0"
LIBERATE parameter "reset_negative_leakage_power" set to "1"
LIBERATE parameter "voltage_map" set to "1"
LIBERATE parameter "pin_based_power" set to "0"
LIBERATE parameter "power_multi_output_binning_mode" set to "1"
LIBERATE parameter "power_subtract_leakage" set to "4"
LIBERATE parameter "subtract_hidden_power" set to "2"
LIBERATE parameter "subtract_hidden_power_use_default" set to "3"
bad value "primary" for parameter
voltage float () Voltage value
while executing
"OptDoOne descriptions state arguments"
(procedure "OptDoAll" line 30)
invoked from within
"OptDoAll desc arglist"
(procedure "::tcl::OptKeyParse" line 10)
invoked from within
"::tcl::OptKeyParse set_vdd $args"
(procedure "set_vdd" line 1)
invoked from within
"set_vdd –type primary vdd VDD_VALUE"
(file "/home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/template/template.tcl" line 1)
invoked from within
"::theRealSource /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/template/template.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 ::theRealSource $args"
(procedure "source" line 3)
invoked from within
"source ${TEMPLATE_FILE}"
(file "/home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/../liberate/tcl/char.tcl" line 21)
Peak memory usage: 394 MB
Peak virtual memory usage: 366 MB
Peak physical memory usage: 27 MB
Wall time : 0.00 hours (2.00 seconds)
LIBERATE exited on cad19 at Mon May 10 22:04:15 2021
Where am I going wrong? Have I configured any of the tcl files wrongly?
thank you so much in advance for your time!