ddt() at a certain timestep in Verilog-A

Hi,

if

electrical [0:n] x_node;
electrical [0:n] d;
parameter real n=5;
real a=1e-9;
genvar i;
//...
for(i=0; i<n; i=i+1) begin
     V(d[i])<+ a*ddt(V(x_node[i]));
end
//...

Is it possible to find V(d[i]) at a certain timestep? How?

Regards,
Ramy