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Accessing data vector generated by a Virtuoso expression in Matlab using adeInfo
Hi,I have been using the improved Virtuoso integration with Matlab (adeInfo etc) (Matlab R2019B, Virtuoso 18.1)I am able to get a waveform from the results database into Matlab for processing ( i.e. of...
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VAR function output slowly
I am using VAR function to get the design variable, but the output generate very slowly.
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modeling output impedance in a file
hello,i am trying to model an LDO as a norton equivalent network. i can run an .ac simulation to get the output impedance vs frequency and export it as a file, but am having a difficult time figuring...
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floating metal check in layout
hello experts,is there some LVS/DRC/ERC checking that we can identify floating metals which doesn't connect to any pins nor devices? looks like ERC only checking floating devices but not the metal...
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avoid local alteration on iterative instances
hello,I am running a monte carlo simulation (local mismatch only) and I would like to skip local alteration on iterative instances. for example, let us consider a current mirror Imaster<2:1> to...
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Transient Violations taking too much disk space
Hello,I am sure this may have come up before but couldn't find this specific thing on the forums.I am trying to run a PLL simulation using transient (liberal) and currently taking up too much space.The...
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ADE L problem
Hello,I am trying to use ADE L to run DC and AC simulation, but when I click "analyses" => "choose", it shows the following error:*Error* (Default-reader-method) generic:asiGetField class:listmy...
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Libraries not imported in the Library manager
Dear guys，I would like to ask a question about the libraries. When we installed Cadence before, the libraries are all well imported. But recently, it seems the following instruction in the "cds.lib"...
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cross probing between layout and schematic
HelloI am using Calibre , start RVE, load svdb. I'd like to be able to select devices or nets in schematic and have them highlight in the layout. How can this be done in RVE? Right now the net...
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annotating parasitics from Calibre PEX netlist to layout or schematic
Hello,If it is possible to cross-annotate parasitic net R, C (coupling cap Cc between nets and C from net to gnd) using Calibre PEX, would someone please tell me how to do so?ThanksHaritha
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noise/jitter transfer function along clock-driven inverter chain
Hi everyone, hope the section is correct.I'm simulating with spectre the inverter chain shown in the figure below where the input signal is a 30GHz sinusoid that is AC coupled to first inverter. My...
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Stability check issue during phase starting with 0 degree
Hi! I'm trying to design buffer amp for specific application, so I want to check stability such as phase margin using an instance 'iprobe'(actually it doesn't matter to use ac simulation). However, the...
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phase noise/vin vs. frequency
Hi all,I have a Phase Interpolator to simulate in Periodic Steady-State (shooting). This circuit synthesizes a clock with digitally-controlled delay on its ouput based on input reference clocks.I would...
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Does MC mismatch simulation reflect best or arbitrary layout ?
Hi,one question regarding MonteCarlo (MC) mismatch simulations is, how the simulation results are related to layout.Does the mismatch simulation reflect the case where the layout is optimized regarding...
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How to properly shutdown virtuoso?
I mean the cds.log, virtuoso.conf, simulstion, and everything.Cdsnameserver, clsbd process, etc.
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Save VHDL variables of specific hierachy
Hello,I'd like to save all VHDL variables in ADE Assembler of a VHDL file in an transient AMS simulation.The VHDL file is referenced inside a verilogams wrapper and marked as "External HDL" in the...
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monte carlo simulation
Hi, For monte carlo simulation, all devices are treated as uncorrelated.there is constraint manager in IC61x to set constraint coefficient between devices, for example OP input stages.is there...
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Reading from a file in Verilog-A
Dear All,To simulate the performance of an analog IC design (using spectre) , I want to "pass" a specific, predefined, sequence of binary data. For this purpose, I have created a "memory" using...
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Question on ADE Assembler (maestro) corner setup
Hi,Could I ask in maestro, how to move design vairables in the corner setup up and down to re-sort them? I know I can delete all variables and rebuilt from scratch or modify the sequence in csv files...
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What is thermal noise called
Hello,My cadence Virtuoso version is IC6.1.8-64b.500.9 and my Spectre simulator version is sub-version 19.1.0.237.isr3.From my understanding sfl stands for the flicker noise of a transistor and what is...
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