Does MC mismatch simulation reflect best or arbitrary layout ?

Hi,

one question regarding MonteCarlo (MC) mismatch simulations is, how the simulation results are related to layout.

1. Does the mismatch simulation reflect the case where the layout is optimized regarding mismatch (e.g. best common centroid layout approach + dummies) ? In this case, a non-optimum layout would cause more/bigger mismatch than simulated.
2. Or does the mismatch  simulation reflect the case of arbitrary placed components all over the wafer (or over a certain layout area)? In this case, an optimized layout (centroid + dummies, etc.) would cause less mismatch than simulated.

For example, if one designs a R2R-DAC and the mismatch-simulation shows that all specifications are fulfilled.

Would a straight forward compact layout (with dummies etc.) be good enough - or does only a best-optimized common centroid layout guarantee these results ?

BR

HoWei