Save VHDL variables of specific hierachy

Hello,

I'd like to save all VHDL variables in ADE Assembler of a VHDL file in an transient AMS simulation.

The VHDL file is referenced inside a verilogams wrapper and marked as "External HDL" in the config view of the testbench.

How is it possible to save all variables in this specific subcircuit / VHDL file?

When I save all nets (Outputs -> save all... -> Save nets -> all), the variables are saved. However, this saves also all analog nets, which results in a huge simulation result and is not an option.