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There are several pwl sources in one file.
Hi.I want to include a pwl file.If there is one pwl source in the file, the value of the pwl file is output as voltage using 'vsource' in 'analogLib'. Already I know this.If there are 100 pwl sources...
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pnoise_pmjitter missing when running sweeps
Hello,I am trying to run a pnoise jitter simulation in ADE Explorer (in Virtuoso ICADV12.3-64b) and I am encountering an issue when sweeping across corners.When I run a single point I am able to get...
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Running worst case corners from ADEXL
Hello,I am trying to verify my design against PVT by running the worst case corners. I have found that I can define my corners in two methods in ADEXL:1. From Single Run, Sweep and Corners : I can...
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Finding the transfer function for same circuit under two different situaton
1. CircuitI am analysing the stability for a ciruit in cadence by breaking the feedback loop. For stability analysis we have to find the Loop gain which is A(s)B, where B is beta factor A(s) =...
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Design of DC motor model in pspice
Hi I want develope basic circuit of DC motor which consist of resistor, inductor and back emf in capture and check its simulation in pspice, for reference I have attached image and link.can some...
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purpose of file "sp.noise.sp"
Hi,During SP analysis of LNA circuit (quite large netlist due to extracted views), the simulation is very slow. I could trace it to a file (sp.noise.sp) in psf folder, which I believe gets written...
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Error when opening library in Abstract Generator
Hi,I'm getting the below error when opening a library in Abstract Generator. The error is related to an information that should be present in the technology file.The error says : The routing direction...
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Modeling a transmission line using the mclin element
HiI am trying to model a transmission line with the mclin/nclin elelment from the rftline lib. I first created the stackup and then reference the stackup element in the mclin instantiation. My...
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Maximum resistance of the lines
Dear friends,Is there a tool to simulate the impact of the resistance from the lines in the circuit performance?I want to obtain the maximum resistance that a line can have without reducing one...
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How to know the END of a Spectre Simulation fired in the Linux terminal.
Dear All,I fired a Spectre Simulation in Linux terminal. (spectre filname.scs).It ran successfully, Is there any way (like some command) by which we can detect the end of the successful or...
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Quantus QRC generates "nan" valued resistors. Spectre throws an error and...
Hi.I'm running Quantus RLCK and I noticed that sometimes it creates on or two "nan" valued resistors (either using ladder-network model or not).This doesn't happen for RC extraction.The problem is that...
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What is the difference between id and ids of a MOS operating parameter
Dear All,Can anybody please tell me what is the difference between id and Ids of a MOS operating parameter shown in operating point list of ADE.Kind Regards.
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How to find the transient operating point of MOS device while simulating...
Dear All,We can find the transient operating point of MOS device (see as below) with non-extracted or pre-layout netlist.But, how it can be done when we are using extracted netlist (spf view of the...
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Regarding including .sp file in cdl
Hi,I want to include a *.sp in a cdl fie by using .INLCUDE.But the calibre is showing that there are errors in cdl.could some body tell me how to include a .sp file in cdl?Thanks,Ganesh Doddipatla.
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Spectre or Symbol View
Hello,What is the appropriate view name to be used in instantiated device component or cell (transistor, resistor, capacitor, inductor, voltage source, and current source)?Symbol or Spectre view? I...
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MC simulation results of copied-but-equal cells are different
Hi,I do have a design (testbench+blocks) and performed MC simulations.Doing the same simulation again will result with same simulation results.Now I had to rename the design (testbench+blocks), so I...
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Parametric simulation in Cadence ADEXL
Hello,I am trying very simple parametric simulation, that is plotting the NMOS I-V characteristics. The simple procedure to do in ADEL is by sweeping the value of VDS from example from 0 to 3.3 in...
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Export regulation when taping out through an oversea foundry
Does anyone know if an export license is required if you tape out a high speed ADC chip using TSMC? The ADC chip, if in production, would be export controlled by the US government. But is a license...
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From ideal switch to CMOS transitor switch
I am currently doing a simulation using an ideal switch from the analoglib with an open resistance of 1Tohm and closed resistance of 1ohm. Also there is a supply (vpulse) given to the switch to define...
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