Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all articles
Browse latest Browse all 4911

Parametric simulation in Cadence ADEXL

$
0
0

Hello,

I am trying very simple parametric simulation, that is plotting the NMOS I-V characteristics.  The simple procedure to do in ADEL is by sweeping the value of VDS from example from 0 to 3.3 in steps of 10m and adding the VGS in the parametric tools from ADEL.

I tried to make this simulation an ADEXL, by creating two variables as VDS and VGS that corresponds to the voltage sources at source and gate respectively. Then in the global variable pan, I defined the same range for VDS and VGS used before in ADEL, I made my test to run only the DC operating point. Now the number of corners are shown 1992, Therefore, this simulation will take a lot of time as compared to the simple setup with ADEL, to make it similar to the ADEL setup I have to sweep the VDS value from the setting of the DC test of the ADE and exclude it from the global variation. 

Is there other better option to run the parametric in ADEXL ?,

By the way in my case I cant use the Group as Parametric set as they have different sweep number of steps

Thank you

Regards


Viewing all articles
Browse latest Browse all 4911

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>