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X-View checker for full design hierarchy for applied sigTypes in all...
Hello,Do you know if there is a full hierarchy x-checker available for sigTypes for Virtuoso, which checks schematics vs symbols throughout the hierachy ?Background/use-case:When running SV-netlister...
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CDF parameter of View - Default Options
Hello,I am sure this has come up before but couldn't find it on the forums.The query is relating to the properties of a VerilogA block. When the block is placed in a schematic and the properties are...
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ICADVM18.1 - using Layout L instead of XL
Hi everyone!We are encountering a problem because we changed from virtuoso of ICADV12.3 to virtuoso ICADVM18.1.With ICADV12 we used Layout L. Actually we have the license for GXL but as far as I...
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dspf_include accept spectre syntax?
Looking for a way to use dspf_include to accept spectre syntax (.scs file). Also, where is dspf_include documented?
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how to create own via in cadence software
hello sir, is there any method to create own via in cadence (IC 6.15)? I know in the cadence there are custom vias that are available to make the layout design.2).when I draw my layout design through...
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How to flatten a hierarchical design?
Hi,I have a hierarchical capture schematic that I need to convert into a flat design and was wondering what are my options to do this how do I go about with this process? Any help would be really...
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extract min and max over corners for every variable step
Hi Everyone, hi Andrew,With ADE-XL I would like to run a simulation over multiple variables values + over multiple corners.For instance in global variables:VAR1 = from/step/to 1/0.1/10VAR2 =...
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layout extraction avoid a specific area
Hi, I am using virtuoso with a foundry CMOS process.I have finished a layout and passed the LVS by Calibre.In the PEX, would we have any way to avoid the parasitic extraction on a specific layout...
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Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso...
A little present for the holiday season - if you're not already subscribed to the Custom IC Blog series, you might want to take a look at this summary of the Virtuosity and Virtuoso Video Diary series...
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How to reduce parasitics from layout
How to reduce parasitics from layout? When i simulate pre-layout and post-layout form of my design there is vast variation in delay and power when i measure. how can I improve my layout design?
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technology file manager
Hi all,I am getting an issue when opening technology file manager.The error is techManagerOpenTechToolBox()*Error* eval: unbound variable - ciwvHelpMenuERRORI am using ICADV12.3-64b.please help...
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Parameters of a FINFET
Hi all,I am new learner of Cadence. While I was performing simulations using FINFET as a device, I found out the voltage across the device using two methods :-1. By taking node voltages difference2....
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Launching ADE L failed
Hi, I am using IC617 to integrate simulator with Virtuoso. I have following warnings and error happens when I am trying to launch ADE L from Schematic Editor window.*Warning* hiCreatePulldownMenu: The...
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[Spectre] multiple dynamic parameters ?
Hi Andrew,We are running under IC6.1.7-64b.500b.14, ADE-XL.I have a very accurate transient simulation to perform (with less than 0.1ps accuracy) but I am drowned into simulation noise, even with...
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making ruler visible from higher hierarchy
hi guys,say i mark something with ruler on cell X which is a sub block of cell Y..i can see the ruler exist in cell X but when i open cell Y i did not see the ruler that was supposed to be in cell X...
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How to create an output expression for given expression using aged and fresh...
Dear Support,I am running Aging simulation using ADE Assembler and want to create an expression, which represents difference of 10yr and stress or fresh results. I am interested in difference between...
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How to sweep multiple params and save the specific param selected from the...
first of all, i am fresh here. and i am happy to be here.recently, i am learning how to use ocn. and i met a question troubled me a lot.simulator('spectre) // design(".../netlist") //...
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Stability factor of differential LNA
Currently designing a differential LNA schematics in virtuoso, my issue is at the output I am using a VCVS. while trying to plot "Kf (stability factor)" it gives no plot, since S12 is zero while using...
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How to get smooth and accurate output waveform without increasing simulation...
Dear All,I was simulating a divider (by-2) extracted circuit @ 17 GHz input frequency using transient analysis.My simulation option was as below:-simulatorOptions options psfversion="1.1.0" reltol=1e-3...
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How to verify LEF vs GDS
Dear forum,I would like to know how I should verify LEF vs GDS to make sure LEF is really synced with the GDS? What Cadence tools do I need to use?Is there any recommended flow for this?Thanks,Norayr...
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