Hello,
Do you know if there is a full hierarchy x-checker available for sigTypes for Virtuoso, which checks schematics vs symbols throughout the hierachy ?
Background/use-case:
When running SV-netlister in the "logical" mode, no netlisting of power/gnd pins is desired. The netlister is sensitive to all sigTypes on schematics and symbols.
In case of a mismatch between symbol and schematic (symbol-terminal "power", but schematic-terminal/net "signal") - even in the hierarchical check & save the mismatch is not flagged. Running logical netsliter here generates a netlist which i.e. has constants assigned to pins. Such a netlist is consisdered as not correct.
In order to avoid it, one needs to fix the mismatches in handcrafted OA.
In case you have such a checker (accepting lib-cell-schematic) as a starting hierarchy and checking all hierarchies/instances incl. schematics and symbols, can you point me to it ? Or is there any other way by running check&save (Virtuoso IC 617/IC18).
Thanks.