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How to set a custom via as default via on VXL/GXL?
Hi Cadence SupportIs there a way to set a custom via as the default via?What I am currently doing:1. On vxl invoke 'Create via"2. Choose via definition3. Adjust rows, columns & cut size spacing to...
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Liberate: Passive Power Calculation
I am characterizing some standard cells (NAND, NOR and D Flip-Flop) using cadence liberate (15.1.4). I am using custom Verilog-A models of the transistor. The characterization is successful with...
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How to save subckt parameters in Spectre
I have device model in subckt form with instance parameter "w". This model has another parameter "r" which is a function of "w".How to save subckt parameter "r" as I sweep parameter "w" in Spectre....
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How to create a BJT symbol in 65nm?
I need to add a BJT to my own circuit. As there is no any BJT schematics in 65nm, I have to draw a layout to create a symbol and use that symbol in my circuit. I would appreciate somebody if let me how...
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How do I send Stability Summary into the Calculator?
Hello,I have an iprobe in a loop of a feedback amplifier, and I am running PSS with PSTB simulation. When simulation finishes, I click on ADE L results >> Analysis "pstb" >> Function...
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Hspice replacement for Switch from AnalogLib
Hello ,I was using switch component from AnalogLib in Spectre (open voltage=0, closed voltage =1 , Open Switch Resistance=1G and Close switch resistance = 1) and I have recently developing a test...
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stimulus test bench
hello sir, sir when I test my circuit in test bench how I can decide the size of two cascaded inverter size that is best of my circuit. Is there any method to decide the size of inverters? please help...
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ADE Assembler - Changing the Maximum Jobs while a Run is In Progress
I am using ADE Assembler in IC617.I was wondering if there is a way to change the Maximum Jobs entry in the Job Policy Setup form, during an active run?I tried updating the parameter during the run,...
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ADE L simulation gave error!
Dear All,I am a new on Cadence Virtuoso, I followed one tutorial and done exactly the same but when I tried to simulate I got following error! generate netlist...Begin Incremental Netlisting Nov 18...
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Cadence Calibre LVS Error with missing connection.
Hi，I got this error in my LVS report. My layout and my schematic both connect good, however the report shows missing connection in my Source Netlist. I wondering where is the Source Netlist circuit...
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Spectre assert output message - printing a variable
Hello,Is it possible in spectre assert statement to print in the warning message a parameter or a variable?For exmaple something like this pmos_vgs assert mod=pch expr="(abs(V(g,s))>1.3)"...
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Error during ADE spectre simulation
Hello,I am facing the problem below after running the simulation from ADE spectre, I made simple CMOS inverter to demonstrate you this error. It looks like ADE is not able to read the model file, I am...
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Does saving more number of nets increase simulation time
Hi All, What is the impact on simulation time with number of nets saved ?Thanks & Regards,Prasad
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Renaming multiple wires using wildcard
Hi,Is there way to rename multiple signals using regular expression.e.g i many have 50 signals with _0 in the name. I want to rename it _1 either using GUI or script.I tried using "net expression" in...
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Small signal analysis during transient, triggered by event
I know about how to run things like ac, stb, and info and set times during transient analysis, but is it possible to run one of these, say ac, at a time determined during the transient simulation...
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Hotel Revenue Management Courses - Ehotel Management
The hotel management is consistently emerging in India from the last years and hotel management has become quite prominent as a career. We also Provide Hotel Revenue Management Courses.The revenue...
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Unbound pins when running Assura LVS in Virtuoso Layout
hello sir, when i draw the layout of the buffer circuit, there is no DRC error but there is one LVS error that occurred which is related to unbound pin.i attached the image of my layout, in this image...
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Cannot EDIF out
Hi, I tried to edif out an inv schematic in library test which contains all devices in inv. But edifout.log shows "Error : Failed to open library test -- exiting". However, I succeeded...
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malias function
Hi, Does ADEXL has the "malias" function as in HSPICE?Ex:.malias nch = nch_mvt(I want to change all 'nch_mvt' in the schematic to 'nch' without modify schematic )thanks.
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Set Subwindow ID for each Trace / Waveform
Hello,I am working with IC 6.1.8. After a transient simulation in ADE Explorer, where I have defined several outputs (signals and expressions), all signal-waveforms are plotted in the same subwindow...
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