I am characterizing some standard cells (NAND, NOR and D Flip-Flop) using cadence liberate (15.1.4). I am using custom Verilog-A models of the transistor. The characterization is successful with accurate delay and leakage power values bit I couldn't understand how passive power is getting calculated. I have following questions that
- Why passive power is in nJ? I believe the tool is integrating the power (for the certain input conditions of the standard cell) over the simulation time. Then essentially passive power is energy ?
- Why passive power is simulation time dependent? For example, I have run characterization for two different simulation time values (simulation time is set in the characterization tcl script) and in both cases the passive power was different while delay and leakage power is same. The change in passive power would also change the dynamic power results in the synthesis tool. How to select this simulation time?
Regards,
Farhan