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Abstract generator pin step issue: no pins created
Hi,I am using AG in IC61. When I ran the pin step for my inverter layout, the warning ABS-502 stated that no pins is created. I don't see anything wrong with my setting of "map text lables to pins" (I...
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Stream in warning
Hi, I have a SRAM memory instance which is generated using a compiler. while streaming it in I am getting the following warning"WARNING (XSTRM-80037): A zero-area polygon was encountered and ignored."...
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setenv LBS_CLUSTER_MANAGER
Hi, Does anyone know how to set LBS_CLUSTER_MANAGER environment varaible? Thanks, Justin
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segment error for symbol
Hello, I wrote a veriloga code for some behavioural modeling. It compiled fine and let me create a symbol. I then instantiated the symbol and tried to sim it with spectre. The spectre...
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probing nets in Virtuoso Schematic isn't recognized in Simvision
Hello,Before running simulation I probe nets in Virtusoso Schematic (key 9), hoping that these net will be recognized by Simvision.But after launching NC-verilog, compiling/netlisting and than...
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Can no plot signals during Monte-Carlo tran simulation
Hi, I can not plot signals during Monte-Carlo analysis run in Virtuoso 6.1.3. After simulation completes simulation results appear in Results Browser. Is there any solution to see signals during...
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Translating IC6 libaries to IC5
Hi,Is there a way to downgrade an IC6 library to IC5? I know it's strange buit in some case it should be the best way to reuse some IP.Regards,Giuseppe
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monte carlo trimmed simulation in adexl (cadence 6)
Hi,Does anyone know how to setup monte carlo simulation under adexl in such way that:- 1st test bench uses tran smulation to find a trimming code for a particular instance (DUT)- 2nd test bench uses dc...
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ASSURA 3.1.6 error message
Hi,I am working with IC.5.1.4 (Cadence version 07/08) together with austriamicrosystems HitKitV3.70. I am trying to run DRC with ASSURA 3.1.6 on my layout but I get the following error message:Reading...
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No width segment in QuickView layout window
Dear membersI'm neophyte of Quickview.Background I've noticed the function "Fade Overlap" of QuickView would be usefull when comparing two layout data DEF for rough visual check, since we used to...
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Modeling and simulation of FinFET in cadence
Hello. I m MTech student. I want to simulate FinFET based digital circuits. But I don't have a FinFET model in cadence. Please help me by providing an equivalent model of FinFET or any other way to...
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Power calculation
I want to calculate overal leakage power of a 6T SRAM. Should I have to calculate leakge power at each node of all transistors?I searched on the Internet and got various ways to calculate leakage...
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cap ground signal 'gndRefNode' cannot be found while running Assura QRC
Dear Experts, Recently we have migrated from Assura RCX to QRC and after running QRC( same way we run RCX) I am facing the following ERRORs:...
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Import from Synopsys IC Compiler to Virtuoso
Hello all, I have a full chip design in Synopsys IC Compiler. I need to import it into Virtuoso. What is the best way to do this? GDSII or something else?Thanks!
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Calibre PEX & PERC execution from command prompt
HI,I would like to know how to execute Calibre PEX & PERC from command prompt ( eg: drc & lvs can be run like calibre -drc/lvs -hier rule_file). Please share if any document available for...
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Automatic Route and Placement
Dear Cadence CommunityHello, I've decided to begin do explore some more Cadence possibilities and I have discovered some extra options such as, Automatic Route which seems to be brilliant but...
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can not generate functional view using nc-verilog
When I use cadence generate verilog model for top simulationopen a schematic , open ade L, choose Launch ->Plugins->Simulation->NC-Verilogthe schematic had sub cells which have 'shematic...
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layout xl automatic routing of the gate
Hi to everyone.I am working at the layout of a cellview and I am using DFM rules. If I edit the properties of transistors I can select to automatically place the contacts on the poly for the gate:...
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Verilog Netlister compatible net-separator in OA ?
Hello,I am trying to find a hierarchical net-separator which works as follows:When you generate a Verilog netlist, it will contain no separator instance, and the net-name of both "shorted" nets is...
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How do I override irunArgs being set by the ADE state when using runams?
I am using a command line AMS simulation flow with the runams command and my own script that builds many, but not all, of the irunArgs I need. The remaining irunArgs come from the ADE state. I have...
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