Power calculation

I want to calculate overal leakage power of a 6T SRAM. Should I have to calculate leakge power at each node of all transistors?

I searched on the Internet and got various ways to calculate leakage power. Please tell me the correct way to calculate the leakage power in any digital circuit in cadence.

By leakage power I mean the power consumed by the transistor when it is in off state.

Thank You.