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Pixelate Custom Curved Polygon According to Grid in Virtuoso Layout Suite L
Hi all,I am working in Cadence Virtuoso Layout Suit L with a design I have previously optimized in another software (CST). The design consists of an archimedean spiral that has infinite resolution...
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Single layer auto-routing
I am trying to design a layout for chip-to-wafer bonding. I need to design a mask that takes the top-level metal pads and routes them to a space outside the chip area (so the new pads can be accessed...
View Articleadexl does not run neither multicorner nor montecarlo simulations
Hello,I heave a recent issue with adexl running multicorner or montecarlo simulation. I am working on IC6.1.8-64b with a TSMC 180nm technology node and the environment has been working perfectly for a...
View ArticleSetting default independent variable in ADE Explorer/Assembler
HiIs there a way to set the default independent variable when you select "Plot All"? I realize it'll be dependent on each assembler/explorer cellview but is there a way to set the default independent...
View ArticleSave certain waveform after simulations end while preserving corner order
Hi, When I save a waveform across corners, the order is changed, how to automate saving of some waveforms after simulations end, moreover preserving corner order.
View ArticleERROR: ADE-5014 in ams simulation
Hi,I got the error in as:ERROR (ADE-5014): Variable 'save': value allpub not found in choices list ("all" "ports" "selected" "none").This error will not block my simulation, but appears many time in...
View ArticlePost Trimming Simulation for Oscillator Circuit
Hello Cadence Support,Could you please tell me how to perform a post-trim simulation on an oscillator circuit? Specifically, post-trim simulation on an oscillator involves:1) Finding an optimal...
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Changing font in "graph summary labels"
HiI am using ICADVM20.1-64b.500.28.I would like to ask, if there is any command or way how to change the font size in graph summary label. Look at the image. I have a lot of histograms and I need...
View ArticlePVS fails with version `GLIBCXX_3.4.26' not found
Hello,I'm trying to make PVS (PVS21.12.000-ISR2_lnx86.tgz) work with IC618 (IC06.18.270_lnx86.tgz), but so far I always with this...
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Importance of "Enable CellView Check" while filling the quantus assura...
Hi, I am trying to run the assura quantus parasitic extraction with the output selected as extracted view. I encountered with a option in the form called "Enable CellView Check". What is the importance...
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Unexpected capacitor values in the av_extracted view file output?
Hi,I ran the extraction with the output as "extracted view". In my schematic I used nmos capacitors with 2 different values of 100fF and 200fF. After running the extraction and viewing the av_extracted...
View ArticleMaestro: Simulation Settings as Output Expressions
Hello,I am trying to check if we can somehow print simulation settings such as "reltol", "gmin", "rebuild_matrix" etc as OUPUT expressions in MAESTRO?I tried VAR("reltol") but it did not...
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Function to take Analog Bits Signals into Digital Bus
Hi,In searching the forums, I found old posts where Andrew Beckett provided code files for abA2DBus, a function that takes an analog bus of signals, e.g., VT("/TreakOscFreq<4:0>) and converts...
View ArticleTitle Block cell issue
So, I have created a title block cell to place in my schematic views. It lists the following:LIB: IlInst~>cellView~>libNameCELL: ilInst~>cellView~>cellNameVIEW:...
View Articledesign/global variables import from veilogA
Hi, is there a way how to import calculated values from VerilogA into design/global variables in ADEXL/Maestro? I need to dynamically change the variables based on my calculations.Is there a way how to...
View ArticleXPM file to layout or symbol view
I am trying to use the .ils file from this old thread. Andrew Beckett does this skill code still work. It was an old thread. When I run the function from the CIW, I get a dialog but when I navigate and...
View ArticleADE Assembler: Get no evaluation for DC sensitivity analysis
Hi,I made an Assembler test settup, which include a sens analysis (for dcOP and dc). I define outputs (like not voltage at net Out) and to which elements I need the sensitivity (like V1). I can run...
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Ramp signal generator in Verilog-A
Hello, I need a ramp signal that starts ramping (e.g., from 500mV to 800mV in 100ns) at the falling edge of the control signal.Here is the snipet which gives something close to what I need but I do not...
View ArticlerexMatchp error when netlist
Hi,I got the error in CIW when netlsit is created from maestro*Error* rexMatchp: argument #2 should be either a string or a symbol (type template = "tS") - nilThis error will not block my simulation,...
View ArticleSimulation startup is too slow
Editing schematic is working fine with good pace. But as I start my simulation it takes a lot of time to just start the simulation, and after simulation gets completed results are also showing very...
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