Ramp signal generator in Verilog-A

Hello,

I need a ramp signal that starts ramping (e.g., from 500mV to 800mV in 100ns) at the falling edge of the control signal.
Here is the snipet which gives something close to what I need but I do not like the way I wrote it, i.e., 100ns is used in the argument for transition().
The result also shows 800mV at the beginning which I do not understand why.
Maybe there is a more proper way to realize this.
the control signal in this example is NREAD_TOA.

    //RAMP
    @(cross(V(NREAD_TOA) - V(VDDA_P1V2)/2, -1))
    begin
    RAMP_START_TON = $abstime;
    RAMP_START_TOFF = RAMP_START_TON + 1n; // I do not like this because I think this is not a proper way.
    end
    @(timer(RAMP_START_TON))
    RAMP_VHIGH = 500m;
    @(timer(RAMP_START_TOFF))
    RAMP_VHIGH = 800m;    

    V(RAMP_START) <+ transition(RAMP_VHIGH, TDELAY, 100n, TFALL); // I do not like this because I think this is not a proper way.