I am trying to design a layout for chip-to-wafer bonding. I need to design a mask that takes the top-level metal pads and routes them to a space outside the chip area (so the new pads can be accessed from the top of the wafer).
I have copied the top-level metal pattern from the original chip into rectangular shapes on my new layout, created layout labels and pins, created a schematic with pad instances on matching nets, and so on. However, when I used the floorplanner to place the pads in the IO rows, they don't seem to be aware of the connectivity (see photo below). To my eye, it looks like the placement planner placed the pad instances randomly and assumed that there were enough routing layers to cross paths. My techfile has only one routing layer, but is there some step I missed to indicate to the floorplanner that the routing is only a single layer?
Can anyone point me to the intended workflow for single layer autorouting like this? To summarize, I have pins with net names, and I want to automatically assign pads and route the signals to pads in IO rows such that only a single layer of metal traces are needed. I am using a license for Virtuoso Layout Suite XL.
Any help is appreciated.
