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1/f corner calculation for noise analyses
I am looking for a way to calculate the 1/f corner of my output noise, found this but not sure if this reflects my question.how to capture 1/f noise in spectre - RF Design - Cadence Technology Forums -...
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portorder not being ignored?
For my next trick.......I'm creating a design top level symbol to be embedded in the pad ring schematic.First: there are three global pins at this level, two of them vbat! and vss! are inputs to the...
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Binding issue with digitally synthesized block
Hello ,I synthesized a digital block from it's .v code and imported the GDS into Virtuoso. I also imported the same .v file into Virtuoso to create schematic corresponding to the .v codeI am seeing...
View ArticleSchematic bus terminals has no corresponding layout bus terminal definition
Hello ,I am facing an issue where the CAS shows "Schematic bus terminals has no corresponding layout bus terminal definition" for all the Buses in the layout (imported using GDS)Will be great if some...
View ArticleLiberate: are only hidden power arcs needed when defining power arcs during...
Hi all,I used command "read_library" and "write_template" to generate a tcl file for a BUFT cell (buffer with enable signal) based on an UMC technology. Among all the power arcs, there seems only...
View ArticleHow to use corner output expression in other corners for a multiple corner sim?
I have two tests in ADE Assembler. The first test runs different corners tt,ss,ff etc. in parallel and outputs a calibration co-efficient expression for each corner. The second test uses the output of...
View ArticleWhy doesn't a non repeating sequence "simple" voltage source exist?
Vpulse, Vbit and Vpwl are ok, if a bit painful to setup for short repeating signals, but why doesn't Cadence implement a more simple Voltage source which would allow truly non regular pulsital...
View ArticleconnectRules for multiple power domain
hello experts,I know we can use connectRules() multiple times. but how we specify which block to use which connectRules()? e.g., dig1 needs 1.8V, dig2 needs 3.3V, dig3 needs 5V.thanks a lot,David
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Layout XL stop layers (again)
According to previous post Layout XL stop layers I should be able to add stop layers to avoid shorting through a MIM cap layer for Layout XL to correctly deal with this in our PDK where the vendor...
View Articleunwrap family
Hi Andrew,An old post mentioned script abUnwrapFamily(). I'm struggling with parsing data from nested sweeps and that script sounds like it might be helpful. I searched but did not get a hit. Is that...
View ArticleIs thre a simulator function that can control the simulator's temperature in...
I'm dong Mixed signal simulation using Xcelium. I need to change temperature over time, I know this can be done in Analysis-transient-dynamicParameter, but this is not convineient for my verificaiton...
View ArticleHow to re-use a setting for Assembler Results Table (Detailed Transposed)?
Hi,I run a huge corner analysis, and need not all outputs, signals, etc. So I disabled the waveforms, etc. and used the mouse to hide many many many columns. However, than virtuoso crashed (maybe from...
View ArticleFinding view name used by current ADE Explorer session
Hello,I am starting a ADE explorer session and would like to know which view it is using via skill e.g it can be maestro or maestro_2 and I am unsure of the best way to do this. Most information we get...
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How to show process corner information inside the plot?
Hello, I think it would be nice if I can show the corner information inside the plot, instead of on the left side.I found that the legend setting has 'inside' option but I cannot find a way to show the...
View Articleiv characteristics of solar cell in cadence virtuoso
Please i need help i want to design iv characteristics of solar cell in cadence virtuoso which am going to implement it with my boost converter circuit that i design based on P&0 MPPT method. i...
View Articleinvalid register number in Layout view
Dear All,I'm not able to see the layout for the available schematic capacitorcapacitor cell instance is displayed in layout it says: "invalid register number Need a valid register number from...
View ArticleDC after Tran
I followed the instructions from the link 9 years ago but it does not work for me now;How to simulate DC sweep after TRAN? - Custom IC Design - Cadence Technology Forums - Cadence CommunityThe tran is...
View ArticleStair waveform based on text file
Dear Sir,How to generate a stair-like or sample-hold waveform basing on a text file with content as following format. It's better if there is a way to build a Verilog-a model for this stair-like...
View ArticleRTT w/impedance chart
Hi,I would like to use the real time tuning (RTT) feature to tune an LC impedance transforming network. My outputs are s11, s22, s21 which are complex. I need for the outputs to be plotted and updated...
View ArticleVerilogA - command: $root
Hello I would like to ask, if there is any way how to use command $root in VerilogA language for current reading in the top cell of schematic? I know I can use $root for reading voltage, is it similar...
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