EMX nport view Noise
I was wondering if there is a document that describes how from a passive network that we run EMX on, the noise is extracted. Is it something like input referred voltage and current noise spectral...
View ArticleGetting the absolute max value using the calculator
I am trying to find the global Y peak value of a graph. Basically the ymax but than also with the posibility of it being negative.Using ymax(abs(expression)) will not cut it as I'd like to preserve the...
View ArticleClik here to view.
ERROR (SFE-23) The instance 'pm0' is referencing an undefined model or...
I'm currently designing a dynamic comparator and would like to get the input refered noise by jitter in the pnoise simulation.And this is my pnoise simulation setup. It turns out the error SFE-23,...
View ArticleFinding and transferring the value of a variable that gives the minimum value...
Hello,I am using Virtuoso version IC6.1.8.My goal is to transfer and assign the output (let's call output_2) of one test (let's call test_1) to one of the variables (let's call var_2) of another test...
View ArticleWhether virtuoso only loads the first .cdsinit file it finds
I read the post https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/37048/when-is-cdsinit-local-loadedIt tells me that the .cdsinit load order...
View ArticleHow to measure transient current in simulation.
Hi,for the active digital block if we want to measure active current with transient simulation then in calculator what function we have to use to measure transient current?
View ArticleClik here to view.
Differce between IC5 & IC6 in pnoise simulation(jitter)
I'm currently designing a dynamic comparator and would like to get the input refered noise by jitter in the pnoise simulation.Previously, the way we used to estimate the input referred noise of the...
View ArticleFET Noise in BSIM4
I am trying to find gamma in a single FET simulation to match current noise density (maybe op from calculator), in^2=4*k*T*gamma*gm. I did spectre -h bsim4 but not sure where to find it if any, found...
View Articlecommon mode level in vcvs
the vcvs in analoglib is by default fully differential (both input and output is differential). Say if i give an input of 1.5V to both input terminals (vcvs having a gain of 1), and I want the same...
View ArticleClik here to view.
Unable to change reference of library from cdsDefTechLib to actual pdk
Hello, When opening a layout view I am seeing the below message post which I don't see any PDK layers in my layout window. I even tried re-referencing library to point to the actual pdk lib but...
View ArticleClik here to view.
Parasitic capacitance of the drain of abutted transistors apparently counted...
Thanks in advance for helping me with this issue:I have a problem with the extracted view of a simple NAND circuit. I am using IC 6.1.8, running the LVS with PVS (19.10) and the extraction with Quantus...
View ArticleClik here to view.
Using 'temperature' as a design variable breaks calcVal functionality
I'm using the calcVal function to use a found trim value from my first test in a second and third test and it works as expected. I've added a fourth test that creates a design variable called...
View ArticleReliability Analysis Tutorial
Is there a Reliability Analysis Tutorial or application note?
View ArticleVoltus 20 getting stuck during DEF import
Hey there,I have a design that I can import without any problems into Voltus 14,16, and 18. However, during the defIn phase in Voltus 20, the tool simply gets stuck with full CPU utilization and never...
View ArticleHow To Add Arguments to systemVerilog Extraction
Im facing several issue/complication when doing C&S on system Verilog view - that I pretty much sure I can solve by adding arguments to the xrun command. I found the solution of creting hdl.var...
View ArticleWhy Jee reduced in a chain of inverters?!!!
Hi,I am running Pnoise (Edge Edge Crossing) o an inverter chain. I have 6 stages of inverters, single-ended, with routing and backannotation in my schematic. When I look at the Jee results, I get weird...
View ArticleCannot Create an auto pin
I have been getting the following warning messages lately and is having trouble to drop pins.If I get lucky, the pin will be dropped after several clicks.*WARNING* (LE-105625): Cannot create an auto...
View ArticleClik here to view.
Efficient labeling method？
Please tell me, for such a repeated gate circuit, each left side must be marked with a VDD label. Every time I type a label, I have to press the "L"(down case) key, enter VDD, and then type on the...
View ArticleThe region of operation of MOS transistor
HI,I am going to design analogue circuit, and I need to show the region of operation for all transistors in the circuit after running the simulation.My issue is: I tried two methods to show the region...
View ArticleClik here to view.
expanding the list of the transistor operating point annotation
Hello,I am using Cadence Virtuoso version 6.1.8-64 bitWhen I run the DC operating point there is limited parameters that I can show on the schematic, in my case only 4 as shown in the image below. How...
View Article