Why Jee reduced in a chain of inverters?!!!

Hi,

I am running Pnoise (Edge Edge Crossing) o an inverter chain. I have 6 stages of inverters, single-ended, with routing and backannotation in my schematic. 

When I look at the Jee results, I get weird results. Here are the Jee numbers

Input clock jitter = 86f

Jee - stage 1 output = 105.5f

Jee - stage 2 output = 105f

Jee - stage 3 output = 115.3f

Jee - stage 4 output = 112.6f

Jee - stage 5 output = 135.9f

Jee - stage 6 output = 124f

What doesn't make sense to me is that Jee of stage 3 was reduced from stage 2 and the same happened to stages 4 and 5. 

I doubled checked my setting with the Cadence tutorial and my Pnoise setting was okay /cfs-file/__key/communityserver-discussions-components-files/38/Sampled_2800_Jitter_2900_-noisetype-in-Pnoise_5F00_1.pdf

I would appreciate it if you could help to understand what is happening here.

Thanks.