For my next trick.......
I'm creating a design top level symbol to be embedded in the pad ring schematic.
First: there are three global pins at this level, two of them vbat! and vss! are inputs to the design. One, vplus! is an I/O created by a regulator.
All three appear in the pin list in a "create cellview from cellview" shown in pic one left pins RHS and top pins LHS.
When I create the symbol, it creates none of the global pins on the symbol as expected, BUT complains that vss! is not present in the symbol portorder despite me setting options as per the Cadence app note so that portorder errors/warnings are not generated.
I checked an old schematic/symbol pair and regenerated its symbol. Hey presto, a portorder warning. This did not happen before, I wonder if it's a version bug, I did update recently.
