Problem with systemVerilog netlister in IC618 which stops with cryptical...
Hello,Did you face this error when running SV netlister in logical mode (no-PG) netlist on a hierarchical schematics with explicit PG-pins in top-, and intermediate hierarchies ? Error...
View ArticleTrim Methodology in Maestro Assembler. The trim value is out of range and the...
The tool versions are below:Virtuoso IC 6.1.8-64b.500.15Spectre 19.1.0.541.isr14I developed a trim procedure in Maestro Assembler using the calcVal() function. Assume a trim range from 0 to 15. If the...
View ArticleParameterizing PSP model card parameters, for ADE parametric Analysis
Hello,If I am using a PSP model in Virtuoso. I have a .scs model file under Spectre>models, with a bunch of model parameters. Am I able to parameterize those model card parameters, so that I can run...
View ArticleSoftware Developer Question
Hello,I am a software developer. I graduated in 2015 with a 3.4 GPA. I worked until 2017 until I had to become a caregiver for a family member. I am ready to rejoin the workforce. I was thinking of not...
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Term Order setup for spice reference files
Hi,I have a simple spice netlist I'd like to use in my simulation. I've copied this cell from another project where I actually created it and used without issues, although I do not remember the steps...
View ArticleADE Datasheet Generation Problems
Using ICADVM 18.10.130I experience a number of problems when creating a datasheet, specifically in trying to control what is plotted.I generally use the "Open Graphs" option having plotted what I want...
View ArticleHow to clear the DRC warning highlights from my layout
Hello,I am using Cadence Virtuoso version IC6.1.8-64b.500.6 and Assura tool for the layout verificationAfter the DRC run and the pointing on the warnings, the relevant area on the layout will be...
View ArticleLicense issue while plotting outputs
When I plot outputs by the ADE L, it pop-up a prompt. It's titled "Next License" and says "License Analog_Design_Environment_L not available. Would you like to run with Virtuoso_Visual_Analysis_XL...
View ArticleAccessing waveform generated by a maestro expression in Matlab using adeInfo
Hi,my question is similar to this 2 year old topic:...
View ArticleSimulation of encrypted spectre netlist
Hi All,With the help of 'spectre_encrypt' was able to encrypt the spectre netlist. But not succesful in simulating this encrypted spectre netlist. Do we need any thing specific to simulate this...
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tags in VXL layout
Hello,I'm putting together a layout in IC6.18 and enjoying many of the new features (over the IC5 I'm used to) but what are the little tags that appear on objects from time to time?Thanks!ken
View Articleis there a way to change the design for multiple tests simultaneously?
clicking RMB on the tests and choosing the design is the way I do it.But this way, I need change the design one by one.selecting multiple tests and change the design does not work.is there a way to...
View ArticleThe Datasheet created by ADE Assembler can be opened only by IE (not even Edge).
The tool versions are below:Virtuoso IC 6.1.8-64b.500.15Spectre 19.1.0.541.isr14Hi,I can create the datasheet in ADE Assembler no problem there. However once the html document is created I can open it...
View ArticleLocation of VXL user guide please
I just spent a frustrating 15 minutes trying to locate the Virtuoso layout XL user guide. You would think it would be just a matter of going to the "Product manuals"section, then custom IC design,...
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Suppression of vias not required in VXL?
I thought the pictured "create via option" form would turn off all of the vias I am not interested in instantiating in the layout, but even though I unchecked them, it seems to make no differencein the...
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Necessary to cover pin in hierarchical layout?
Why is it necessary to touch the pin in a sub-block in VXL for "show incomplete nets" to recognize the connection? The tool recognizes the net as being connected to the pin, so why isn't simply...
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VXL and inherited connections?z
I have a schematic, predominantly analog with vss as negative supply. I have a single logic gate instantiated from a ddk with vss! as it's inherited supply. In simulation, I use netset a couple layers...
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How to move to the new Virtuoso?
It seems that the new Virtuoso is already available in my place.I tried these lines below from .cshrc but after running virtuoso, it is still open the old one.Apologize for this very basic question.
View ArticleError Quantus PVS Extraction
Dear Cadence Help,I am trying to run Quantus PVS Extraction on a layout with only a symbol view. (No schematic)I have a cdl netlist which I use to run PVS-LVS with the option to 'Create Quantus QRC...
View Articleocean measure success stories or guide?
Is anyone aware of a good guide on using ocean measures in ADE Explorer or Assembler that includes all the weird quirks and limitations and maybe highlights some success stories? I've tried several...
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