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Problem with systemVerilog netlister in IC618 which stops with cryptical message on a digital schematics in Virtuoso

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Hello,

Did you face this error when running SV netlister in logical mode (no-PG) netlist on a hierarchical schematics with explicit PG-pins in top-, and intermediate hierarchies ? 

Error _hnlCheckIfBusHasAnyNonSupplySigType: argument #1 should be a database object (type template = "d") - nil
ERROR (OSSHNL-411): Stopping netlisting due to SKILL error while formatting devices. To bypass this
check, set the environment variable oss.core stopNetlistingOnFormatterError

I miss a detailed message on the root-cause, and it looks like an internal call in the SKILL-env.

The reference schematic uses power/ground/signal properties in the schematics for nets and ports. Toplevel and intermediate hierarchies have explicit PG pins.

I am not sure if switching off the Formatter is a good idea. So, any comments ?

Thanks in advance

Kind regards

Greg


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