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Listing MOSFET parameters from model
Hi all.Is there a way to get all MOSFET parameters from model like in picture below for "MN0" as a list of strings?Best regards,Dragan
View ArticleFunction to skip start of a signal
For calculating certain quantities, e.g. rms voltage, I would like to skip the first, say, 10m of a signal.Surprisingly I did not find any function which does this (like "cut" or so). In frequency...
View ArticleFinding leakage current paths
Hello,I am using Virtuoso's 6.1.8 release. I am simulating a circuit to find possible leakage current paths in it when the power supplies are connected but various parts of the circuit are disabled...
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The generated datasheet is (almost) empty
I am trying to generate datasheet but the generated datasheet (xml file) only contains the name of the model libraries and global variable.I have tried it when using circuit from Virtuoso® ADE...
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plotting output expression with "all" evalType from GUI using the generated...
My setup works ok from GUI.Now I am trying to run all of them using the generated OCEAN file.So, how can I plot output expression, especially those with "all" evalType, from GUI using the generated...
View ArticleBonding Wire in Cadence Virtuoso
HelloI am using the Cadence Virtuoso tools version IC6.1.8-64b.500.6, and now trying to make a chip prototype.I am on the level of bonding the chip I/O pads to the selected package pins. My problem is...
View ArticleMaestro file become very large
I have been accumulating tests in one maestro file (45MB).It is taking quite sometimes to open and do simulation, especially when using Run Plan.I thought it is just like that because I put so many...
View ArticleIs that OK to use clsdb from different version of cadence tool
Hi,I'm current using network machine "nc grid" for job submission and frequently bumped into below error message:*WARNING* file /nfs/proj/sires/sidisp/user/wjguo/WARD_N7/CDS.log.28 cls: Unable to...
View ArticleCan I use an ADE-Explorer license for an older version of Cadence?
I am trying to access an older design that was done on Cadence version IC6.1.6-64b.500.10. My University no longer has an ADE-XL license, only ADE-Explorer, so I get license errors when I try to open...
View Articlecadence installation issue
We are trying to install and configure cadence in our system.I have installed it using iscape.I am getting the following error.2022/01/25 17:15:07 WARNING This OS does not appear to be a Cadence...
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Converting a pspice model to schematic/spectre (max, table etc)
Hello,I would like to have this pspice circuit as a sub circuit in virtuoso:.subckt ccm-dcm1 1 2 3 4 5 params: L=1 fs=1E6Et 1 2 value={(1-v(u))*v(3,4)/v(u)}Gd 4 3 value={(1-v(u))*i(Et)/v(u)}Ga 0 a...
View Articlewhere the measurement results of across "all" are saved?
I have in my output some measurements with EvalType "all" and would like to know the save location.where the measurement results of across "all" are saved?
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Layout XL : Connectivity - Update Function
Hi All,Suppose in a schematic I named a wire "A" and then did the layout, later on, i changed the name of the particular net to say "B".Now when i do connectivity- update-Components & Nets-Update...
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Importing gds stream data of the assembly housing packages
Hello I am trying to import the gds stream data of my assembly housing packages, My problem is that I fail to attach it to the layer table of my PDK, what happens is that the library of the packages is...
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Problem with terminals definition in a spice component
Hi, I have to integrate in spectre discrete models of transistor. I followed this guide...
View ArticleCan Verilog-A macro names be swept in Corners Setup of ADE Assembler for...
Tried adding -va,define VAR("macro_name") in the command line options in Setup->Environment in the test editor but simulations failed to start with VAR() there.
View ArticlePick a specific voltage value from a wave and save it [OCEAN]
Hello!I'm new into OCEAN and skill, and I have a question regarding the use of output. I'm running a simulation for a pixel array with a loop. The loop changes the illumination power and saves the...
View Articlemulticore AMSD run
Hi I would like to know if the following is do able . Cadence version : IC 6.1.8I am running a top level AMSD run with spectre X and xcelium for the digital . I have acess to an 8 core machine. Is it...
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Checking for LUP and HVESD on cell-level DRC run
Hi Cadence,From my previous tape-out run, my DRC runs on sub-circuit cells did not check for LUP (Latch-up) and HVESD (High-voltage ESD) errors until I ran DRC on chip-level design. Then I was faced...
View ArticleBoolean operations in Virtuoso Layout Editor
Hi, I'm wondering if there is a way to simply perform logical actions on groups of shapes in Virtuoso Layout Editor.Specifically: I checked a random unrelated graphics editor, and it allows Union (OR),...
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