Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all articles
Browse latest Browse all 4962

Can Verilog-A macro names be swept in Corners Setup of ADE Assembler for Spectre simulations?

$
0
0

Tried adding -va,define VAR("macro_name") in the command line options in Setup->Environment in the test editor but simulations failed to start with VAR() there.


Viewing all articles
Browse latest Browse all 4962

Latest Images

Trending Articles



Latest Images

<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>