Checking for LUP and HVESD on cell-level DRC run

Hi Cadence,

From my previous tape-out run, my DRC runs on sub-circuit cells did not check for LUP (Latch-up) and HVESD (High-voltage ESD) errors until I ran DRC on chip-level design. 

Then I was faced with hundreds of LUP and HVESD errors near to the submission deadline. (Please refer to the screenshot below):

So I went back to each sub-circuit block and re-ran DRC, but LUP and HVESD errors still wouldn't appear on sub-circuit level DRC runs. They only appear on the full chip-level DRC run.

Is there any way for me to check for LUP and HVESD errors on sub-circuit level DRC runs, instead of chip-level, so I can find out the errors quicker and fix them during my sub-circuit designs?

Please let me know if this is something possible.

Thank you for your attention,

Jin