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analog digital output average mean value
Hello,I have 4 bit analog digital output. By averaging output, I can not precise result because tools take analog signal. and since analog signal have changes since temperature and little edge...
View ArticleDRC Cadence
Hi, I use XFAB 0.18um technology.while doing simple DRC Run of an simple inverter Layout. I am getting the following error:XH018 Assura Design Rules file version 8.1.1 updated on 210106 X-FAB Design...
View ArticleSet ignoredesigchangesduringrun locally / per session / per maestro cell
Hi,When creating testbenches that run for several days, one would like to ignore any design changes (like using the method described here:...
View ArticleDo you have some recommendations？
Hello, I wanted to use STM32 in my projects but I haven't found a great beginner's guide. Do you have some recommendations？ Thank you.
View ArticleCoplanar wavewguide with GND plane
I have to simulate with spectreRF a 2.4GHz LNA including the effect of the PCB lines. The RF input signal is provided through a coplanar waveguide with gnd plane underneath.I see that the coplanar...
View ArticleverilogA
I created verilogA in cadence and then write my code as seen below but ı get error "extract failed for cellview" why?`include "disciplines.vams" // N-bit Analog to Digital Converter module adc (out,...
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ERROR (ASSEMBLER-5011) and high memory usage after some long simulations
After some repeated long simulations, especially when using Run Plan, I tend to get this error.So far, restarting Cadence solves it, and I would like to know if there is better way.I use this version...
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How to measure node to node capacitance?
Hi everyone,is there a way to measure node-to-node capacitance in version IC6.1.8-64b.500.14? For instance in following feature "A" to "VSS". I mean, I want to measure the equivalent capacitance of the...
View ArticleLocating a result value from montecarlo run table in Cadence Virtuoso
Hello,I am using Cadence Virtuoso version IC6.1.8-64b.500.6,1. I have run the Montecarlo of my designed amplifier over 200 samples plus voltage and temperature range, hence the table results are very...
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Dynamic paramters "temp" doesn't work? (Solver = Ultrasim, transient analysis)
Hi,I am doing mixed signal verification, when I use spectre as analog solver, dynamic paramters in transient analysis works.While when I use ultrasim as analog solver, dynamic parameters doesn't works,...
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cannot specify instances during Monte Carlo setup
I used this setting before on other simulation and it was working just fine.Somehow I have this problem right now.Is there any thing that I need to check?I found this in the user guide.When I use only...
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Saving Assistants' location in Schematic Editor
Hi,I would like to work with the Property Editor docked in the bottom part of my schematic canvas.Every time I open a new schematic, I take this Assitant and place where I like to have it.I was...
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Seal-Ring DRC errors
Hello, I have some issues with the seal-ring design. We are working on XFAB XH035 µm technology and using Cadence tools version IC6.1.8-64b.500.6 with Assura layout package. We have installed the seal...
View ArticleTwo step trimming in Maestro Assembler. Difficulty encountered trying to...
The tool versions are below:Virtuoso IC 6.1.8-64b.500.15Spectre 19.1.0.541.isr14I used a maestro Assembler view to perform a two step trimming procedure followed by the main_test simulation. The...
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Term Order setup for spice reference files
Hi,I have a simple spice netlist I'd like to use in my simulation. I've copied this cell from another project where I actually created it and used without issues, although I do not remember the steps...
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View ArticleVerilogA loop generate constructs not defining multiple sub modules
Hi,I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bitI am using very simplified codes here (empty modules) to simplify the problem statement. Similar behavior is happening with...
View ArticleOption nullmfactorcorrelation for MonteCarlo mismatch simulation
Hi,I am using a m-factor on instances (for example a cell containing transistors) to model parrallel instances instead of using instances with buses that would slow down simulations.I expect to see...
View ArticleVirtuoso recovery from license server interruption?
If the connection to the license server gets interrupted, Virtuoso will say "Virtuoso has lost connection to the license servers and will become unresponsive in 5 minutes. Save your data now and then...
View ArticleUsing Virtuoso without ADE explorer
Hi I am new to custom IC design and cadence tools. I have made some basic circuit in Virtuoso schematic and test bench for it. We don't have licence for ADE Explorer and assembler. I wonder if there is...
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