verilogA

I created verilogA in cadence and then write my code as seen below but ı get error "extract  failed for cellview" why?

`include "disciplines.vams"

// N-bit Analog to Digital Converter

module adc (out, in, clk);
    parameter integer bits = 8 from [1:24];	// resolution (bits)
    parameter real vmin = 0.0;			// minimum input voltage (V)
    parameter real vmax = 1.0 from (vmin:inf);	// maximum input voltage (V)
    parameter real td = 0 from [0:inf);		// delay from clock edge to output (s)
    parameter real tt = 0 from [0:inf);		// transition time of output (s)
    parameter real vdd = 5;			// voltage level of logic 1 (V)
    parameter real vss = 0;			// voltage level of logic 0 (V)
    parameter real thresh = (vdd+vss)/2;	// logic threshold level (V)
    parameter integer dir = +1 from [-1:1] exclude 0;
    						// 1 for trigger on rising edge
						// -1 for falling
    localparam integer levels = 1<<bits;
    input in, clk;
    output [bits-1:0] out;
    voltage in, clk;
    voltage [bits-1:0] out;
    integer result;
    genvar i;

    analog begin
        @(cross(V(clk)-thresh, dir) or initial_step) begin
	    result = levels*((V(in) - vmin))/(vmax - vmin);
	    if (result > levels-1)
	        result = levels-1;
	    else if (result < 0)
	        result = 0;
	    else
	end

	for (i=0; i<bits; i=i+1)
	    V(out[i]) <+ transition(result & (1<<i) ? vdd : vss, td, tt);
    end
endmodule