Hi,
I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bit
I am using very simplified codes here (empty modules) to simplify the problem statement. Similar behavior is happening with much more complex VerilogA modules. This is why I am asking in the first place. I am mentioning this as a disclaimer for the fact that the codes may seem not to do any useful function.
Here is the problem,
When using the loop generate construct inside my parent instantiating module (test_parent) to repeatedly instantiate child modules (test1) and (test2), only the first one (test1 in this situation) is recognized, and have the "ahdl_include" statement generated for it in the attached netlist. However, the second one defined (test2 in this situation) is not recognized nor an "ahdl_include" is generated for it in the netlist.
The attached netlist doesn't have a corresponding "ahdl_include" for (test2), and the attached simulation output log is showing a problem recognizing a "defined model" for it. It is ignored for some reason.
I thought I could instantiate several modules the way I am doing. It is done in a similar fashion in the LRM to build an interconnect model comprised of several RC sections. Am I missing something? How can I make sure both modules are instantiated correctly.
Other things I tried:
- When both modules are reversed in order of their definition, similar behavior is happening, but now with (test1) instead.
- When two for loops are used instead of one, with each one doing instantiation for one of the two modules, similar behavior persists.
Ahmed
VerilogA code for test_parent
community.cadence.com/.../test_5F00_parent_5F00_va.txt
VerilogA code for test1
community.cadence.com/.../test1_5F00_va.txt
VerilogA code for test2
community.cadence.com/.../test2_5F00_va.txt
Generated netlist
community.cadence.com/.../8802.netlist.txt
Part of the output log of a simple simulation showing the errors
community.cadence.com/.../out_5F00_log.txt