Why the tstab and PSS simulations differ in terms of frequency and vrms voltage?
Hi,I have been simulating the VCO, the frequency and voltage calculated from the tsab simulation varies from the PSS simulation? Why is that so?
View ArticleRun QRC using commd under batch mode
Hi I using cadence version 6.1.8, may I know do I need any license to run QRC using command?please advice.regardsFaisal
View ArticleIBIS model from Virtuoso
Hi All,can anyone give any insights on if there is a way to generate IBIS model of an IC design from Virtuoso itself perhaps from the Spectre netlist ?It can be done is other external tools but I wish...
View ArticleProblem in running QRC Quantus in Cadence Virtuoso
Hello,We Newley installed our PDK, when I try to run the QRC I receive the following error message,Is it harmful to ignore ?Thank you very much
View ArticleHow to customizing library manager menus
I tried to add a custom menu the library manager, and can't get it working. It looks to me like the cdsLibMgr.il file is not being loaded. I tried adding this line to it, but nothing shows up in the...
View ArticleLVS with backend kit
I'm trying to LVS a design made using a backend kit. There's main part of the design was created in the analogue flow which lvs's as every cell has schematics.The top level of the chip has some...
View ArticleGenus - Hierarchy
Hi,I am building my circuit which involves a top level and several sub-modules.I am interested in details about these sub-modules, but after the synthesis (syn_generic), the hierarchy is lost and I...
View ArticlePrint statements with subcircuits
Hello, I have a question regarding spectre netlist languageI know If I have a circuit containing MOSFETs, I can use a print statement to save specific parameter value to a file with the following...
View ArticleWhite Noise simulation for MOS transistor
Hello,How is it possible to determine the white noise of transistors from simulation?I know how to determine the noise at the output of transistors for flicker and shot noise but not for white...
View ArticleIntrinsic and extrinsic capacitances from simulation
Hello,In DC simulation it is possible to save DC operating point parameters to determine extrinsic and intrinsic capacitances. For example, CGG = cgg + cgsol + cgdol + cgbol, CGB = cgb + cgbol, CDD =...
View ArticleCalibre view generation encountered a fatal error
Hi,Has anyone experienced this type of error? I cannot generate the calibre view. The calibre log file states that my library can't be found although the parasitic extraction is performed.
View ArticleDoes IC618 work in RHEL 8.2?
Hi,I have checked the compatibility matrix document. I’m trying to understand when it says IC618 runs at RHEL 8, does it mean it works with the minor releases of RHEL for example 8.2? Second thing is,...
View ArticleIC617 Running Issue at RHEL8.2
Hello,First of all, I understand that RHEL 8.2 is not a supported version for IC617. But, as I already installed the Hotfix_IC06.17.722_lnx86.sdp (I haven't installed the base) and later figured out...
View ArticleADE: is it possible to select DSPF nodes for PNOISE simulation?
Hi! I am trying to run a triggered PNOISE analysis on a extracted design using a DSPF view, but I'm unable to specify in ADE the triggering nodes.In my original PNOISE settings (run over the pre-layout...
View ArticleHow to group design variables and switch between them for different tests in...
Hi,I am trying to run different simulations(tests) for the same schematic in same ADEXL view. In other words, I have a single schematic and ADEXL view. In ADEXL view, I have couple simulations...
View ArticleHow to evaluate the variable in a maestro measurement expression and not...
I am trying to measure some signals and it is constantly evaluating it as a string and not capturing it as a variableExample:This scenario works perfectly --> maeAddOutput(strcat("read" "avg") title...
View Articlelost file
Hello everyone!Iv designd an ALU as part of school home work, after creat all small parts Iv created the ALU - schmatic and layout.After the file had pass DRC and LVS with no errors i tried to have a...
View ArticleLVS reads pins incorrectly
Hello,I am running an Assura LVS test on my layout and receive some mismatch errors like the following:Schematic Net: S[0]S *1 of device_X:Swap1 ALayout Net: S[0]L *1 of device_X:Swap0...
View ArticleERROR ADEXL 7514
Hi,Every time when I open the assembler, and try to view the existed result, terminal shows me the ERROR ADEXL 7514 as below, also my assembler window is stuck. What is the root cause and how to remove...
View ArticleTransformer and Mutual Coupling
Dear All, I want to use a transformer in both cadence spectre and virtuoso,My used Technology does not have its own Transformer.How I can Activate the mutual coupling between two Technologu's spiral...
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