I'm trying to LVS a design made using a backend kit.
There's main part of the design was created in the analogue flow which lvs's as every cell has schematics.
The top level of the chip has some standard cell logic cells that have no schematic view, and a digital block created in encounter (this has verilog code associated with it)
I've tried to black box the cells in calibre, but I'm afraid my knowledge of how to do that isn't up to snuff.
Can anyone lend me some advice on how to LVS such a design?