Mutual Coupling
Dear All,I want to build a transformer.I use "mind" tool from analoglib Library to assign a mutual coupling between two ideal spiral inductors in schematic.I think it fails with other technology's...
View ArticlePin placement is giving me trouble
Good evening,i am trying to automatically place pins in the layout XL enviroment using the Place->Analog->adjust cell pins. But as you can see in the picture below i am not obtaining great...
View ArticleMonte Carlo Error when simulating larger array (smaller array runs just fine)
I have an array of 64 by 64 simple cells, the cells consist of no more than 10 transistors and their output is either VDD or GND (with mismatch). My problem is when I simulate for 64 rows (with each...
View ArticleADE XL Save Options
Hi everyone,I hope to get your help with the ADE XL save options. The story is: I didn't change the simulation results save directory, then our lab's disk full. My teacher asked me to change the...
View ArticleCreate a netlist of an extracted view, create a "netlist"/"spectre"/whatever...
Hi,I need to use an extracted view as a subcell in a testbench, and put a resistor of this extracted view in parameter in order to optimize my design with the post-layout parasitics; would you see a...
View ArticleModGen tool is violating the DRC rules
HelloI am using the ModGen (Module Generator)from Cadence Virtuoso version IC6.1.8After creating the matched layout array from ModGen and using it in the layout editor, after running the DRC I see that...
View ArticleEdit Synchronous clone
I am trying to clone resistor chains so they can be all matched.In the generate clones form I do a search. The tool finds the instances in the pattern mostly.It selects instance name in other chain....
View ArticleIs there a way to resume a cadence virtuoso that got stuck?
Hi,Is there a command or a way to resume a Cadence virtuoso that got stuck due to some process? I am fine with killing the simulation/process that's running on virtuoso but I don't want to kill the...
View ArticlePlot using waveVsWave function
Hi,I've setup an Assembler session with one test and one dcOP analysis.The schematic is pretty basic, just a single transistor for which vgs, L and W are being swept.Let's say that I...
View ArticleFinfet Stacked CMOS oppoint problem
Hi All,I'm trying to use "Measuring Stacked-FET Parameters" function of SPECTRE16, in order to find oppoint, such as gm, gds.. for stacked Finfet. I have done all settings specified in spectre user...
View ArticleCan Liberate take encrypted spice netlist?
Hi,I want to know if Liberate can take encrypted spice netlist, or if this standard cell characterization tool can take encrypted spectre netlist?Thanks.
View ArticleHow to export top schematic + all sub schematics?
I am new to Cadence. I was given a design to work in which has many sub-schematics in its hierarchy. I want to export to PDF, PNG or whatever image format the schematic for the top and each...
View ArticleTransient noise analysis - Simulation very slow
Hi all,I would like to run a transient noise analysis in a mixed signal system. For better estimation of the noise bandwidth of interest I ran an AC noise analysis of my system in steady state. I found...
View ArticleSpectre model aliasing
HiI have a (I think) really simple question - our spectre models use a name for our transistors but an IP provider used a different name for our MOS that it uses and I was wondering if there's a way to...
View ArticleAssura QRC error
Hi everyone!Recently I'm using Assura and I can run drc and lvsHowever, qrc always fails. The log file gives errors as follows:I run the cmd terminal>$QRC_HOME/tools/bin/RCXspice -args in a...
View Articlewould it be possible to copy a component or block inside a symbol when you...
In schematic, would it be possible to copy a component or block inside a symbol when you descend into a block and copy it out?Like first you use "shift + E" to descend inside a block and then use "c"...
View ArticleNoise Contribution and Simulation in Cadence.
Hi, I would like to know how to simulate noise simulation in cadence, I am trying to simulate a simple current mirror and trying to find how much noise it contributes to the circuitry. I biased the...
View Articlebindkey to open calibre nmDRC & nmLVS & PEX
Hi, is there bindkey to open nmDRC, nmLVS and PEX in Calibre from layout view?Thanks for your help.
View ArticleIs there some way to calculate power consumption of blocks in a schematic...
Is there some way to calculate power consumption of blocks in a schematic automatically?Power consumption is calculated by voltage* rms(current) over a specific period.I saw the code for I0:pwr but...
View ArticlePlot horizontal line (e.g. limit line) in ViVa
Hi,I want to add a horizontal line to the ViVa plot (e.g. for a transient plot).I do not want to use the "h" button in ViVa.I want to define the y-value of the line via output expressions as a function...
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