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A problem with ports mismatch in LVS
HiI am working by xfab 0.35um technology to design an op-amp but I have encountered with a problem. When I want to run LVS through calibre an error is appeared "different numbers of ports". The ports...
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Can't edit instances
Hello,I am not able to edit instances such as transistors. I have never encountered such as thing before. It is a 7nm Arizona State University 7nm Finet Predictive PDKMy virtuoso version is:Version...
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Defining viva background color changed from IC6.1.7 to 6.1.8?
Back when I was using IC6.1.7 I had the following in my .cdsinit to get everything on a white background as my default:envSetVal("viva.rectGraph" "background" 'string "white")envSetVal("viva.rectGraph"...
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export snp s parameter from multiple conditions in ADE explorer
Hi all,I am run sp simulation over different DC bias condition in ADE explorer. For example, I have 4 bias conditions. I can check plots by sweeping the biases. How can I export 4 snp in one...
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How to handle XL compliance and LVS reduction together
Hi,I am using virtuoso XL and trying to be 100% XL compliant. Now I have created 2 instances in the schematic for a device. The connections are all the same but finer and multiplier differ.MN3 W=1.818...
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Cadence Virtuoso Technology Files and Libraries
Hi,I want to design some circuits in virtuoso. Schematic and layout are included of my design. I need simulation libraries(5V nmos and pmos) of schematic, also layout technology files. How can i take...
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System Verilog outputs connected in parallel causes voltage division
Hi,for functional verification we started to model our cells and top-level blocks in SystemVerilog.For logic signals we are using the "logic' datatype.For the analog signals we are using the 'real'...
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Error during Monte Carlo stimulation
I want to run a Monte-Carlo stimulation, but I get the error 'database disk image is malformed'. How can I solve this error?
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Spectre stopping on symbol
While generating a Spectre netlist, is there any way to force a cell to be netlisted as empty? I am planning to replace the cell with a separate .scs model file, but I need the connections to be made...
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Importing Verilog-A code
Hi All,I wish you are well. I have imported a Verilog-A code of a specific model of a transistor in Cadence. I could create transistor symbol and run simulations for a few days. However, after a while,...
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apply jitter to oscillator model from external file
Hi,I'm trying to add jitter to an oscillator model. The jitter (TIE) is based on a phase noise profile and is stored in a separate file. My thinking is that every oscillator edge, it reads the jitter...
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unwanted symbol instance in the layout
Hello.I am user of IC6.1.7 with GPDK180_v3.3.From time to time when I started to run DRC, unexpected schematic symbols are added, which results in VDB error. Of course, when such a case occurs, I...
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Error when doing Monte Carlo Simulation
Hi all,I am doing Monte Carlo simulation with IC617 and TSMC 180nm PDK. I am using ADE explorer to do the simulation. But the simulation failed with the following error:ERROR (EXPOLRER-5052): Monte...
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Fatal error when use ADE L to simulate veriloga blocks.
Hi,I am using 6.1.6 to do some design and I try to use some VerilogA blocks, for example the blocks in ahdlLib and some customized blocks, in my simulation. But it meets an error showing below. The...
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Error in abutment of transistor Pcells
Hi,I am getting the below message when trying to abut two transistor Pcells, inside a Modgen.*WARNING* (LX-2206): Unable to abut the following two instances: 'ModgenDummy_0_0_Modgen_1' (instance of...
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Pnoise can not plot Jc(k)
Hi,I have done the PSS and Pnoise simulation of a RC oscillator. I want to use Jc(k) function to show the cycle jitter as belowBut cadence shows me the error, saying unable to plot expression ...I...
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Update PCELL Parameters in APR
Can I get more clarifications on the option " Update Pcell Params " in Auto P&R?
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PSD Calculation of a Pulse Train after a Transient Simulation
Dear Community,I performed a very simple PSD calculation for a periodic pulse train that is generated using Verilog-A modelling. The pulse train has fixed high voltage 1V and low voltage 0V, fixed duty...
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Create VDR Labels/Markers from Simulation Voltages
I am trying to use the simulation-based Voltage Dependent Rules (VDR) flow for the 1st time.Question: If I saved the Vmin/Vmax dataset from a EAD-enabled simulation of a TB, it creates 'constraint'...
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low voltage SRAM Design
I am working on project and i need help regarding this topic:"Evaluation of Low Voltage Performance Enhancement techniques in SRAMs and its physical design (with annotated capacitances)"
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